📄 ixdp2400_pci.c
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/* ixdp2400_pci.c
---------------------------------------------------------------------------
Copyright (c) 2002, 2003 Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors
may be used to endorse or promote products derived from this software
without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------
system: IXDP2400
subsystem: BootMonitor
author: lagarwal
revisions:
--------------------------------------------------------------------------
*/
#include <pkgconf/hal.h>
#include <pkgconf/system.h>
#include CYGBLD_HAL_PLATFORM_H
#include CYGHWR_MEMORY_LAYOUT_H
#include <cyg/infra/cyg_type.h> // base types
#include <cyg/infra/cyg_trac.h> // tracing macros
#include <cyg/infra/cyg_ass.h> // assertion macros
#include <cyg/hal/hal_io.h> // IO macros
#include <cyg/hal/hal_if.h> // calling interface API
#include <cyg/hal/hal_arch.h> // Register state info
#include <cyg/hal/hal_intr.h> // Interrupt names
#include <cyg/hal/hal_cache.h>
#include <cyg/hal/hal_ixdp2400.h> // Hardware definitions
#include <cyg/io/pci_hw.h>
#include <cyg/io/pci.h>
#include <cyg/hal/cfg_utility.h>
#include <cyg/hal/ntb_srom_util.h>
#include <redboot.h>
#include <flash_config.h>
// define this to leave Slave in reset (in single flash mode)
//#define DONT_INIT_SLAVE
externC cyg_uint32 ext_osc_freq;
cyg_pci_device slave_dev_info;
extern struct board_config *board_config_data;
extern struct _config config;
externC char __rom_data_start[], __ram_data_start[], __ram_data_end[];
void ntb_init(void)
{
cyg_pci_device_id dev_id = CYG_PCI_NULL_DEVID;
if(!cyg_pci_find_device(NTB_VENDOR_ID, NTB_DEVICE_ID, &dev_id))
{
printf("Couldn't find 21555\n");
return;
}
if(strap_options_val() & CFG_PCI_BOOT_HOST)
{
#if 0
// check to see if SROM is blank
if(read_srom_byte(0) == 0xFF)
{
char srom_data[] = {0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x86, 0x80, 0x00, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0xF0, 0xFF, 0xFF, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00,
0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0xF1, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x08, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00};
printf("Found blank 21555 SROM. Going to program it..\n");
// if blank then program default data
// default data program 1M of DS_IOMEM1 and DS_MEM3 BAR and 10M of DS_MEM3 BAR
write_srom((char *)srom_data, sizeof(srom_data));
}
#endif
printf("Mapping CSR for mapping from host\n");
// master's CSR and SDRAM will be mapped using downstream BAR 1 and 2 respectively
cyg_pci_write_config_uint32(dev_id, DS_IOMEM_1_TBASE, (*(PCI_CSR_BAR_REG) & ~0xF));
//#define MAP_SRAM
#ifdef MAP_SRAM
printf("Mapping SRAM for mapping from host\n");
cyg_pci_write_config_uint32(dev_id, DS_MEM_2_TBASE, (*(PCI_SRAM_BAR_REG) & ~0xF));
//#define TEST_MAP_SRAM
#ifdef TEST_MAP_SRAM
printf("Init SRAM for testing\n");
*((volatile cyg_uint32 *)(0x80000000)) = 0x12345678;
*((volatile cyg_uint32 *)(0x80000004)) = 0x12345678;
#endif
#else
printf("Mapping SDRAM for mapping from host\n");
cyg_pci_write_config_uint32(dev_id, DS_MEM_2_TBASE, (*(PCI_DRAM_BAR_REG) & ~0xF));
#endif
//#define TEST_21555_PRI
#ifdef TEST_21555_PRI
#define NTB_PRI_COMMAND 0x44
#define DSTREAM_MEM_1_PRI_BAR 0x18
#define DSTREAM_MEM_2_PRI_BAR 0x1C
#define DSTREAM_MEM_3_PRI_BAR 0x20
#define DSTREAM_MEM_1_SEC_BAR 0x58
#define DSTREAM_MEM_2_SEC_BAR 0x5C
#define DSTREAM_MEM_3_SEC_BAR 0x60
#define CONFIG_CSR 0x92
#define UPSTREAM_CONFIG_ADDR 0x88
#define UPSTREAM_CONFIG_DATA 0x8C
#define NTB_PRI_IDSEL 17
// enable IO and Mem transactions from primary side
cyg_pci_write_config_uint16(dev_id, NTB_PRI_COMMAND, CYG_PCI_CFG_COMMAND_IO |
CYG_PCI_CFG_COMMAND_MEMORY | CYG_PCI_CFG_COMMAND_MASTER);
// enable upstream config cycles and self addressing
cyg_pci_write_config_uint16(dev_id, CONFIG_CSR, (3 << 9));
// assign PCI address to downstream BARs
cyg_pci_write_config_uint32(dev_id, UPSTREAM_CONFIG_ADDR, ((1 << NTB_PRI_IDSEL) | DSTREAM_MEM_1_PRI_BAR));
cyg_pci_write_config_uint32(dev_id, UPSTREAM_CONFIG_DATA, 0x80000000);
cyg_pci_write_config_uint32(dev_id, UPSTREAM_CONFIG_ADDR, ((1 << NTB_PRI_IDSEL) | DSTREAM_MEM_3_PRI_BAR));
cyg_pci_write_config_uint32(dev_id, UPSTREAM_CONFIG_DATA, 0x80100000);
cyg_pci_write_config_uint32(dev_id, UPSTREAM_CONFIG_ADDR, ((1 << NTB_PRI_IDSEL) | DSTREAM_MEM_2_PRI_BAR));
cyg_pci_write_config_uint32(dev_id, UPSTREAM_CONFIG_DATA, 0x81000000);
#endif
}
else
{
printf("Mapping CSR for mapping from host\n");
// slave's CSR will be mapped using downstream BAR3
cyg_pci_write_config_uint32(dev_id, DS_MEM_3_TBASE, (*(PCI_CSR_BAR_REG) & ~0xF));
}
}
void slave_ixp_init(void)
{
int i, temp;
int slave_sdram_passed = 1;
/* PCI unit does a byte swapping by default. But we don't want to swap bytes when copying into slave's memory.
So set these bits so that PCI unit doesn't do byte swapping. */
*(PCI_CONTROL_REG) |= (PCI_CONTROL_BE_DEO | PCI_CONTROL_BE_DEI | PCI_CONTROL_BE_BEO | PCI_CONTROL_BE_BEI);
// SDRAM, SRAM and CSR bars are mapped in master's pci mem space.
// first BAR is CSR, second is SRAM and third is SDRAM
*(PCI_ADDR_EXT_REG) = (slave_dev_info.base_address[CSR_BAR] & 0xE0000000) >> 16;
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + PCI_CONTROL_FRM_PCI)) |= (PCI_CONTROL_BE_DEO | PCI_CONTROL_BE_DEI | PCI_CONTROL_BE_BEO | PCI_CONTROL_BE_BEI);
// check to see if slave has flash or not
if((*(volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + STRAP_OPTIONS_FRM_PCI) & CFG_PROM_BOOT))
{
printf("Dual flash system detected\n");
}
else
{
// slave doesn't have flash. So, start slave init
printf("Single flash system detected\n");
// enable outbound pci int. from xscale
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + PCI_OUT_INT_MASK_FRM_PCI)) &= XSIM;
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + PCI_OUT_INT_MASK_FRM_PCI));
#endif
// set the upper bits for pci mem and io transactions
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + PCI_ADDR_EXT_FRM_PCI)) = 0x0;
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + PCI_ADDR_EXT_FRM_PCI));
#endif
// slave pci init is complete. So start accepting pci transactions
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + IXP_RESET0_FRM_PCI)) |= INIT_COMP;
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + IXP_RESET0_FRM_PCI));
#endif
// now I need to config SDRAM/SRAM also. So, that I can download image in SDRAM.
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + DDR_RCOMP_IO_CONFIG_FRM_PCI)) = DDR_RCOMP_IO_CONFIG_VAL;
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + DDR_RCOMP_IO_CONFIG_FRM_PCI));
#endif
// setup operating freq. for SDRAM/SRAM interface
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + CCR_FRM_PCI));
temp &= ~(0xF00FF);
if(ext_osc_freq == 100000000)
{
temp |= ((CCR_150MHZ_DIVISOR << 16) | (CCR_150MHZ_DIVISOR << 4) | CCR_150MHZ_DIVISOR);
}
else
{
temp |= ((CCR_150MHZ_DIVISOR << 16) | (CCR_200MHZ_DIVISOR << 4) | CCR_200MHZ_DIVISOR);
}
#else
temp = *CCR_REG;
#endif
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + CCR_FRM_PCI)) = temp;
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + CCR_FRM_PCI));
#endif
hal_delay_us(1000); // 1ms
// now config SDRAM interface
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + DDR_RDDLYSEL_RECEN_FRM_PCI)) = DDR_RDDLYSEL_RECEN_VAL;
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + DDR_RDDLYSEL_RECEN_FRM_PCI));
#endif
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + DDR_RX_DLL_FRM_PCI)) = DDR_RX_DLL_VAL;
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + DDR_RX_DLL_FRM_PCI));
#endif
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + DDR_RX_DESKEW_FRM_PCI)) = DDR_RX_DESKEW_VAL;
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + DDR_RX_DESKEW_FRM_PCI));
#endif
// cr0_dstrengthsel
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + CR0_DSTRENGTHSEL_FRM_PCI)) = 0x036db6db;
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + CR0_DSTRENGTHSEL_FRM_PCI));
#endif
// cr0_ddqrcomp
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + CR0_DDQRCOMP_FRM_PCI)) = 0;
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + CR0_DDQRCOMP_FRM_PCI));
#endif
// cr0_dctlrcomp
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + CR0_DCTLRCOMP_FRM_PCI)) = 0;
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + CR0_DCTLRCOMP_FRM_PCI));
#endif
// cr0_drcvrcomp
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + CR0_DRCVRCOMP_FRM_PCI)) = 0;
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + CR0_DRCVRCOMP_FRM_PCI));
#endif
// cr0_dckercomp
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + CR0_DCKERCOMP_FRM_PCI)) = 0;
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + CR0_DCKERCOMP_FRM_PCI));
#endif
// cr0_dcsrcomp
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + CR0_DCSRCOMP_FRM_PCI)) = 0;
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + CR0_DCSRCOMP_FRM_PCI));
#endif
// cr0_dckrcomp
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + CR0_DCKRCOMP_FRM_PCI)) = 0;
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + CR0_DCKRCOMP_FRM_PCI));
#endif
// cr0_dx8x16ckecscksel
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + CR0_DX8X16CKECSCKSEL_FRM_PCI)) = 0x11111111;
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + CR0_DX8X16CKECSCKSEL_FRM_PCI));
#endif
// cr0_rcompprd
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + CR0_RCOMPPRD_FRM_PCI)) = 0;
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + CR0_RCOMPPRD_FRM_PCI));
#endif
// cr0_digfil
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + CR0_DIGFIL_FRM_PCI)) = 0;
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + CR0_DIGFIL_FRM_PCI));
#endif
/* Program DDR DQ/DQS pull-up and pull-down Slew Lookup table registers */
/* (cr0_ddqpslew0 - cr0_ddqpslew3) and (cr0_ddqnslew0 - cr0_ddqnslew3) */
for(i = (DRAM_CH0_BASE_FRM_PCI + 0x150); i <= (DRAM_CH0_BASE_FRM_PCI + 0x188); i += 8)
{
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + i)) = 0xcccccccc;
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