post.h

基于ecos的redboot

/* post.h
---------------------------------------------------------------------------
                 Copyright (c) 2002, 2003 Intel Corporation
						 All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer. 
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. 
* Neither the name of Intel Corporation nor the names of its contributors
may be used to endorse or promote products derived from this software
without specific prior written permission. 
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                      
---------------------------------------------------------------------------
system: IXDP2400
subsystem: BootMonitor
author: gvaddadi
revisions:
--------------------------------------------------------------------------
*/
#include <cyg/hal/hal_ixdp2400.h>       // Platform specific hardware definitions

//I2C defines -start
#define CLOCK 0x80
#define DATA  0x40

#define I2C_WRITE_MODE 		0x00
#define I2C_READ_MODE		0x01
#define DELAY_I2C			50
#define I2C_INIT_BIT		0x04 

//I2C defines -end

#define SCRATCH_TEST_END_ADDR	SCRATCHPAD_BASE+ 0x100 //256 bytes
#define SDRAM_TEST_END_ADDR		0x100000 //1MB

//macro to initialise the UART	
.MACRO  START_UART reg0, reg1
	ldr	\reg1, =IXP2400_UART_ADDR				/* base address of UART */
	
	ldr \reg0, =0x80808080						/* enable access to divisor registers */
	str	\reg0, [\reg1, #UART_LineControl]
	
	ldr \reg0, =DEFAULT_BAUD_DIVISOR
	str	\reg0, [\reg1, #UART_DivisorLatchLSB]
	ldr	\reg0, =0x00000000
	str	\reg0, [\reg1, #UART_DivisorLatchMSB]
	
	ldr	\reg0, =0x03030303                  	/* 8 data, 1 stop bit, no parity */
	str	\reg0, [\reg1, #UART_LineControl]       /* also disables access to divisor regs */
	
	ldr	\reg0, =0x40404040
	str	\reg0, [\reg1, #UART_InterruptEnable]   /* no IRQs just yet */
	
	ldr	\reg0, =0x01010101
	str	\reg0, [\reg1, #UART_FIFOControl]       /* set bit 0 */
	
	ldr	\reg0, =0x07070707
	str	\reg0, [\reg1, #UART_FIFOControl]       /* turn FIFOs on */
	
	ldr	\reg0, =0x00000000                      /* clear the THRE bit for TI UARTs */
	str	\reg0, [\reg1, #UART_LineStatus]
.ENDM

//macro for uart Tx
.MACRO UARTTx reg0, reg1, reg2
	ldr \reg1, =IXP2400_UART_ADDR                /* base address of UART */
30:
	ldr \reg2, [\reg1, #UART_LineStatus]
    tst \reg2, #0x20
    beq 30b                                      /*  and wait for the all clear */
    str \reg0, [\reg1, #UART_Transmit]           /* Tx character in reg0 */
.ENDM

/* ----------- I2C protocol driver macros-begin ----------- */

// Macro to write to GPIO registers
.macro GPIO_REG_WRITE	reg0, reg1, greg, data
	ldr		\reg1, =\greg	//load the GPIO register addr 
	ldr		\reg0, =\data	//load the value to be written
	str		\reg0, [\reg1]	//write to the register
.endm

//Macro to read the level on a particuler GPIO pin
.macro GPIO_REG_READ  reg0, reg2, gpioreg, bitmsk	
	ldr		\reg0, =\gpioreg	//load the GPIO register to be read
	ldr		\reg2, [\reg0]		//read the register value
	ldr		\reg0, =\bitmsk		//load the bit mask
	and		\reg2, \reg2, \reg0	//store the bit value
.endm

//macro that generates delay
.macro I2C_DELAY ntimes, reg8
	ldr	\reg8, =\ntimes
10:
	subs	\reg8, \reg8, #1
	bpl		10b
.endm

//macro to generate START condition in a i2c transaction
.macro I2C_START reg0, reg1
	//SDA=1, SCL=1
	GPIO_REG_WRITE \reg0, \reg1, GPIO_PDCR, DATA
	I2C_DELAY DELAY_I2C, r8
	GPIO_REG_WRITE \reg0, \reg1, GPIO_PDCR, CLOCK
	I2C_DELAY DELAY_I2C, r8

	//SCL=1, SDA=0 . since SCL is alreday 1 , i am setting SDA to 0
	GPIO_REG_WRITE \reg0, \reg1, GPIO_PDSR, DATA
	I2C_DELAY DELAY_I2C, r8

	//SCL=0;SDA=0 since SDA is already low, i am setting SCL to 0
	GPIO_REG_WRITE \reg0, \reg1, GPIO_PDSR, CLOCK
	I2C_DELAY DELAY_I2C, r8
.endm

//macro to generate a STOP condition in a i2c transaction
.macro I2C_STOP reg0, reg1
	//SCL=0, SDA=0
	GPIO_REG_WRITE \reg0, \reg1, GPIO_PDSR, DATA
	I2C_DELAY DELAY_I2C, r8

	//SCL=1, SDA=0
	GPIO_REG_WRITE \reg0, \reg1, GPIO_PDCR, CLOCK
	I2C_DELAY DELAY_I2C, r8

	//SCL=1,SDA=1
	GPIO_REG_WRITE \reg0, \reg1, GPIO_PDCR, DATA
	I2C_DELAY DELAY_I2C, r8
.endm

.macro I2C_WRITEBIT reg0, reg1, reg2
	GPIO_REG_WRITE \reg0, \reg1, GPIO_PDSR, CLOCK
	I2C_DELAY DELAY_I2C, r8

	tst \reg2, #0x80
	beq 12f
	GPIO_REG_WRITE \reg0, \reg1, GPIO_PDCR, DATA
	b 13f

12:
	GPIO_REG_WRITE \reg0, \reg1, GPIO_PDSR, DATA

13:
	I2C_DELAY DELAY_I2C, r8
	GPIO_REG_WRITE \reg0, \reg1, GPIO_PDCR, CLOCK
	I2C_DELAY DELAY_I2C, r8
	GPIO_REG_WRITE \reg0, \reg1, GPIO_PDSR, CLOCK
	I2C_DELAY DELAY_I2C, r8
	GPIO_REG_WRITE \reg0, \reg1, GPIO_PDCR, DATA
.endm

//macro to put 8 bits on the i2c bus
.macro I2C_WRITEBYTE data, reg0, reg1, reg2
	//load data to be written into reg2
	ldr \reg2, =\data
	ldr r7, =0x0	// used by for loop

14:
	I2C_WRITEBIT \reg0, \reg1, \reg2
	mov		\reg2, \reg2, LSL #1
	add		r7, r7, #1
	cmp		r7, #8
	bne		14b
	
	GPIO_REG_WRITE \reg0, \reg1, GPIO_PDCR, DATA
.endm

.macro I2C_READBIT reg0, reg1, reg2
	GPIO_REG_WRITE \reg0, \reg1, GPIO_PDSR, CLOCK
	I2C_DELAY DELAY_I2C, r8
	GPIO_REG_WRITE \reg0, \reg1, GPIO_PDCR, CLOCK
	I2C_DELAY DELAY_I2C, r8
	GPIO_REG_READ \reg0, \reg1, GPIO_PLR, DATA

	tst \reg1, #DATA
	bne 10f
	ldr \reg2, =0x0
	b 11f

10:
	ldr \reg2, =0x1

11:
	GPIO_REG_WRITE \reg0, \reg1, GPIO_PDSR, CLOCK
	I2C_DELAY DELAY_I2C, r8
.endm

//macro to get 8 bits from the i2c bus
.macro I2C_READBYTE reg0, reg1, reg2, reg4
	//initilaize r4 with zero, this will contain the read byte
	ldr		\reg4, =0x0
	ldr		r7, =0x0	// use by for loop
228:
	I2C_READBIT \reg0, \reg1, \reg2
	orr		\reg4, \reg4, \reg2
	mov		\reg4, \reg4, LSL #1
	add		r7, r7, #1
	cmp		r7, #7
	bne		228b

	I2C_READBIT \reg0, \reg1, \reg2
	orr		\reg4, \reg4, \reg2
.endm

.macro I2C_DEVICE_BUSY slave, reg0, reg1, reg2
	ldr r6, =0x0	// use by while loop
	ldr \reg2, =0x1	// set as busy
15:
	I2C_START \reg0, \reg1
	I2C_WRITEBYTE \slave, \reg0, \reg1, \reg2
	I2C_READBIT \reg0, \reg1, \reg2
	cmp \reg2, #0x0	// check if busy
	beq 17f			// branch if not busy

	I2C_STOP \reg0, \reg1
	add r6, r6, #1
	cmp r6, #4
	bne 15b
17:
.endm

//macro that implements the i2c protocol to read a byte from the i2c device
.macro I2C_READ slave, addr, reg4
	I2C_DEVICE_BUSY \slave, r0, r1, r2
	cmp r2, #0x0
	bne 18f

	I2C_WRITEBYTE \addr, r0, r1, r2
	I2C_READBIT	r0, r1, \reg4
	I2C_DELAY DELAY_I2C, r8

	I2C_START r0, r1
	I2C_WRITEBYTE \slave|I2C_READ_MODE, r0, r1, r2
	I2C_READBIT r0, r1, \reg4

	I2C_READBYTE r0, r1, r2, \reg4
	ldr r2, =0x80
	I2C_WRITEBIT r0, r1, r2
	I2C_STOP r0, r1
	b 18f

	.ltorg
18:
.endm

.macro I2C_WRITE slave, addr, data
	I2C_DEVICE_BUSY \slave, r0, r1, r2
	cmp r2, #0x0
	bne 19f

	I2C_WRITEBYTE \addr, r0, r1, r2
	I2C_READBIT	r0, r1, r4
	I2C_DELAY DELAY_I2C, r8

	I2C_WRITEBYTE \data, r0, r1, r2
	I2C_READBIT	r0, r1, r4
	I2C_STOP r0, r1
	b 19f

	.ltorg
19:
.endm

.macro I2C_INIT0
	/* initially at power up SDA has pull down because it is used as strap pin.
	 * the PCI_ARB strap pin which is GPIO 2 should be driven high inorder to 
     * have a pull up on SDA line. This is required by this board design
     */
    
    /*configure GPIO 6 as output*/
	GPIO_REG_WRITE r0,r1, GPIO_PDSR, I2C_INIT_BIT

	/*drive this pin high*/
	GPIO_REG_WRITE r0,r1, GPIO_POSR, I2C_INIT_BIT

#if 0
	/*configure pin 7 and 6 to be output*/
	GPIO_REG_WRITE r0,r1, GPIO_PDSR, (CLOCK|DATA)
#endif

	/*make the output level on pins gpio 6 and 7 low*/
	GPIO_REG_WRITE r0,r1, GPIO_POCR, (CLOCK|DATA)

	/*make pins 6 and 7 as input during init*/
	GPIO_REG_WRITE r0,r1, GPIO_PDCR, CLOCK

	I2C_DELAY 10, r8
	
	GPIO_REG_WRITE r0,r1, GPIO_PDCR, DATA
	
	I2C_DELAY 0x1000, r8

.endm

//End of macros for I2C


//macro that does the POST		
.macro POST
	ldr	r0, =SLAVE_POST_FLAG_LOC
	ldr	r1, =0x0