hal_ixdp2400.h

基于ecos的redboot

#define QDR_RCMP_SETUP_CONTROL_OFF	0x300 
#define QDR_RCMP_PMOS_OVER_OFF		0x30C 
#define QDR_RCMP_NMOS_OVER_OFF		0x310
#define QDR_RCMP_PMOS_NMOS_OVER_OFF	0x314

/* dram registers */
#define DRAM_CSR_BASE				0xD0009000

#define DU_CONTROL_OFF				0x0
#define DU_ECC_TEST_OFF				0x18
#define DU_INIT_OFF					0x20
#define DU_CONTROL2_OFF				0x28
#define DDR_RCOMP_IO_CONFIG_OFF		0x3C0
#define DDR_RDDLYSEL_RECEN_OFF		0x3C8
#define DDR_RX_DLL_OFF				0x650
#define DDR_RX_DESKEW_OFF			0x688
#define CR0_FRCSMRCOMP_OFF			0x100
#define CR0_DSTRENGTHSEL_OFF		0x130
#define CR0_DDQRCOMP_OFF			0x148
#define CR0_DCTLRCOMP_OFF			0x190
#define CR0_DRCVRCOMP_OFF			0x1D8
#define CR0_DCKERCOMP_OFF			0x228
#define CR0_DCSRCOMP_OFF			0x2B0
#define CR0_DCKRCOMP_OFF			0x338
#define CR0_DX8X16CKECSCKSEL_OFF	0x220
#define CR0_RCOMPPRD_OFF			0x108
#define CR0_DIGFIL_OFF				0x118
#define CR0_SLEWPROGRAMMED_OFF		0x128
#define CR0_OVRRIDEH_OFF			0x138
#define CR0_OVRRIDEV_OFF			0x140
#define CR0_JT_CONFIG_OFF			0x3C0


#define DU_CONTROL					(DRAM_CSR_BASE + DU_CONTROL_OFF)
#define DU_ECC_TEST					(DRAM_CSR_BASE + DU_ECC_TEST_OFF)
#define DU_INIT						(DRAM_CSR_BASE + DU_INIT_OFF)
#define DU_CONTROL2					(DRAM_CSR_BASE + DU_CONTROL2_OFF)
#define DDR_RCOMP_IO_CONFIG			(DRAM_CSR_BASE + DDR_RCOMP_IO_CONFIG_OFF)
#define DDR_RDDLYSEL_RECEN			(DRAM_CSR_BASE + DDR_RDDLYSEL_RECEN_OFF)
#define DDR_RX_DLL					(DRAM_CSR_BASE + DDR_RX_DLL_OFF)
#define DDR_RX_DESKEW				(DRAM_CSR_BASE + DDR_RX_DESKEW_OFF)
#define CR0_FRCSMRCOMP				(DRAM_CSR_BASE + CR0_FRCSMRCOMP_OFF)
#define CR0_DSTRENGTHSEL			(DRAM_CSR_BASE + CR0_DSTRENGTHSEL_OFF)
#define CR0_DDQRCOMP				(DRAM_CSR_BASE + CR0_DDQRCOMP_OFF)
#define CR0_DCTLRCOMP				(DRAM_CSR_BASE + CR0_DCTLRCOMP_OFF)
#define CR0_DRCVRCOMP				(DRAM_CSR_BASE + CR0_DRCVRCOMP_OFF)
#define CR0_DCKERCOMP				(DRAM_CSR_BASE + CR0_DCKERCOMP_OFF)
#define CR0_DCSRCOMP				(DRAM_CSR_BASE + CR0_DCSRCOMP_OFF)
#define CR0_DCKRCOMP				(DRAM_CSR_BASE + CR0_DCKRCOMP_OFF)
#define CR0_DX8X16CKECSCKSEL		(DRAM_CSR_BASE + CR0_DX8X16CKECSCKSEL_OFF)
#define CR0_RCOMPPRD				(DRAM_CSR_BASE + CR0_RCOMPPRD_OFF)
#define CR0_DIGFIL					(DRAM_CSR_BASE + CR0_DIGFIL_OFF)
#define CR0_SLEWPROGRAMMED			(DRAM_CSR_BASE + CR0_SLEWPROGRAMMED_OFF)
#define CR0_OVRRIDEH				(DRAM_CSR_BASE + CR0_OVRRIDEH_OFF)
#define CR0_OVRRIDEV				(DRAM_CSR_BASE + CR0_OVRRIDEV_OFF)
#define CR0_JT_CONFIG				(DRAM_CSR_BASE + CR0_JT_CONFIG_OFF)

#define DU_CONTROL_REG				((volatile cyg_uint32 *)DU_CONTROL)
#define DU_ECC_TEST_REG				((volatile cyg_uint32 *)DU_ECC_TEST)
#define DU_INIT_REG					((volatile cyg_uint32 *)DU_INIT)
#define DU_CONTROL2_REG				((volatile cyg_uint32 *)DU_CONTROL2)
#define DDR_RCOMP_IO_CONFIG_REG		((volatile cyg_uint32 *)DDR_RCOMP_IO_CONFIG)
#define DDR_RDDLYSEL_RECEN_REG		((volatile cyg_uint32 *)DDR_RDDLYSEL_RECEN)
#define DDR_RX_DLL_REG				((volatile cyg_uint32 *)DDR_RX_DLL)
#define DDR_RX_DESKEW_REG			((volatile cyg_uint32 *)DDR_RX_DESKEW)

/* interrupt registers */
#define IRQ_CSR_BASE				0xD6000000

#define IRQ_STATUS_OFF				0x8
#define IRQ_ENABLE_SET_OFF			0x10
#define IRQ_ENABLE_CLR_OFF			0x18

#define IRQ_STATUS_REG				((volatile cyg_uint32 *)(IRQ_CSR_BASE + IRQ_STATUS_OFF))
#define IRQ_ENABLE_SET_REG			((volatile cyg_uint32 *)(IRQ_CSR_BASE + IRQ_ENABLE_SET_OFF))
#define IRQ_ENABLE_CLR_REG			((volatile cyg_uint32 *)(IRQ_CSR_BASE + IRQ_ENABLE_CLR_OFF))

/* pci config registers */
#define PCI_CFG_REG_BASE			0xDE000000

#define PCI_CMD_STAT_OFF			0x4
#define PCI_CSR_BAR_OFF				0x10
#define PCI_SRAM_BAR_OFF			0x14
#define PCI_DRAM_BAR_OFF			0x18
#define PCI_RCOMP_OVER_OFF			0x60

#define PCI_CMD_STAT				(PCI_CFG_REG_BASE + PCI_CMD_STAT_OFF)
#define PCI_CSR_BAR					(PCI_CFG_REG_BASE + PCI_CSR_BAR_OFF)
#define PCI_SRAM_BAR				(PCI_CFG_REG_BASE + PCI_SRAM_BAR_OFF)
#define PCI_DRAM_BAR				(PCI_CFG_REG_BASE + PCI_DRAM_BAR_OFF)
#define PCI_RCOMP_OVER				(PCI_CFG_REG_BASE + PCI_RCOMP_OVER_OFF)

#define PCI_CMD_STAT_REG			((volatile cyg_uint32 *)PCI_CMD_STAT)
#define PCI_CSR_BAR_REG				((volatile cyg_uint32 *)PCI_CSR_BAR)
#define PCI_SRAM_BAR_REG			((volatile cyg_uint32 *)PCI_SRAM_BAR)
#define PCI_DRAM_BAR_REG			((volatile cyg_uint32 *)PCI_DRAM_BAR)
#define PCI_RCOMP_OVER_REG			((volatile cyg_uint32 *)PCI_RCOMP_OVER)

/* pci local csrs */
#define PCI_LOCAL_CSR_BASE			0xDF000000

#define PCI_OUT_INT_MASK_OFF		0x34
#define MAILBOX_0_OFF				0x50
#define MAILBOX_1_OFF				0x54
#define MAILBOX_2_OFF				0x58
#define SRAM_BASE_ADDR_MASK_OFF		0xFC
#define DRAM_BASE_ADDR_MASK_OFF		0x100
#define PCI_CONTROL_OFF				0x13C
#define PCI_ADDR_EXT_OFF			0x140
#define XSCALE_INT_STATUS_OFF		0x158
#define XSCALE_INT_ENABLE_OFF		0x15C

#define PCI_OUT_INT_MASK			(PCI_LOCAL_CSR_BASE + PCI_OUT_INT_MASK_OFF)
#define MAILBOX_0					(PCI_LOCAL_CSR_BASE + MAILBOX_0_OFF)
#define MAILBOX_1					(PCI_LOCAL_CSR_BASE + MAILBOX_1_OFF)
#define MAILBOX_2					(PCI_LOCAL_CSR_BASE + MAILBOX_2_OFF)
#define SRAM_BASE_ADDR_MASK			(PCI_LOCAL_CSR_BASE + SRAM_BASE_ADDR_MASK_OFF)
#define DRAM_BASE_ADDR_MASK			(PCI_LOCAL_CSR_BASE + DRAM_BASE_ADDR_MASK_OFF)
#define PCI_CONTROL					(PCI_LOCAL_CSR_BASE + PCI_CONTROL_OFF)
#define PCI_ADDR_EXT				(PCI_LOCAL_CSR_BASE + PCI_ADDR_EXT_OFF)
#define XSCALE_INT_STATUS			(PCI_LOCAL_CSR_BASE + XSCALE_INT_STATUS_OFF)
#define XSCALE_INT_ENABLE			(PCI_LOCAL_CSR_BASE + XSCALE_INT_ENABLE_OFF)

#define PCI_OUT_INT_MASK_REG		((volatile cyg_uint32 *)PCI_OUT_INT_MASK)
#define MAILBOX_0_REG				((volatile cyg_uint32 *)MAILBOX_0)
#define MAILBOX_1_REG				((volatile cyg_uint32 *)MAILBOX_1)
#define MAILBOX_2_REG				((volatile cyg_uint32 *)MAILBOX_2)
#define SRAM_BASE_ADDR_MASK_REG		((volatile cyg_uint32 *)SRAM_BASE_ADDR_MASK)
#define DRAM_BASE_ADDR_MASK_REG		((volatile cyg_uint32 *)DRAM_BASE_ADDR_MASK)
#define PCI_CONTROL_REG				((volatile cyg_uint32 *)PCI_CONTROL)
#define PCI_ADDR_EXT_REG			((volatile cyg_uint32 *)PCI_ADDR_EXT)
#define XSCALE_INT_STATUS_REG		((volatile cyg_uint32 *)XSCALE_INT_STATUS)
#define XSCALE_INT_ENABLE_REG		((volatile cyg_uint32 *)XSCALE_INT_ENABLE)

/* csr addresses as seen from PCI */
#define GLOBAL_CONTROL_BASE_FRM_PCI	0x4A00

#define MISC_CONTROL_FRM_PCI		(GLOBAL_CONTROL_BASE_FRM_PCI + MISC_CONTROL_OFF)
#define IXP_RESET0_FRM_PCI			(GLOBAL_CONTROL_BASE_FRM_PCI + IXP_RESET0_OFF)
#define CCR_FRM_PCI					(GLOBAL_CONTROL_BASE_FRM_PCI + CCR_OFF)
#define STRAP_OPTIONS_FRM_PCI		(GLOBAL_CONTROL_BASE_FRM_PCI + STRAP_OPTIONS_OFF)

#define SLOW_PORT_CSR_BASE_FRM_PCI	0x80000

#define SCRATCH_BASE_FRM_PCI		0xF0000

#define QDR_CH_BASE_FRM_PCI			0xF9000

#define DRAM_CH0_BASE_FRM_PCI		0xFD800

#define DU_CONTROL_FRM_PCI			    (DRAM_CH0_BASE_FRM_PCI + DU_CONTROL_OFF)
#define DU_ECC_TEST_FRM_PCI			    (DRAM_CH0_BASE_FRM_PCI + DU_ECC_TEST_OFF)
#define DU_INIT_FRM_PCI				    (DRAM_CH0_BASE_FRM_PCI + DU_INIT_OFF)
#define DU_CONTROL2_FRM_PCI			    (DRAM_CH0_BASE_FRM_PCI + DU_CONTROL2_OFF)
#define DDR_RCOMP_IO_CONFIG_FRM_PCI	    (DRAM_CH0_BASE_FRM_PCI + DDR_RCOMP_IO_CONFIG_OFF)
#define DDR_RDDLYSEL_RECEN_FRM_PCI	    (DRAM_CH0_BASE_FRM_PCI + DDR_RDDLYSEL_RECEN_OFF)
#define DDR_RX_DLL_FRM_PCI			    (DRAM_CH0_BASE_FRM_PCI + DDR_RX_DLL_OFF)
#define DDR_RX_DESKEW_FRM_PCI		    (DRAM_CH0_BASE_FRM_PCI + DDR_RX_DESKEW_OFF)
#define CR0_FRCSMRCOMP_FRM_PCI			(DRAM_CH0_BASE_FRM_PCI + CR0_FRCSMRCOMP_OFF)
#define CR0_DSTRENGTHSEL_FRM_PCI		(DRAM_CH0_BASE_FRM_PCI + CR0_DSTRENGTHSEL_OFF)
#define CR0_DDQRCOMP_FRM_PCI			(DRAM_CH0_BASE_FRM_PCI + CR0_DDQRCOMP_OFF)
#define CR0_DCTLRCOMP_FRM_PCI			(DRAM_CH0_BASE_FRM_PCI + CR0_DCTLRCOMP_OFF)
#define CR0_DRCVRCOMP_FRM_PCI			(DRAM_CH0_BASE_FRM_PCI + CR0_DRCVRCOMP_OFF)
#define CR0_DCKERCOMP_FRM_PCI			(DRAM_CH0_BASE_FRM_PCI + CR0_DCKERCOMP_OFF)
#define CR0_DCSRCOMP_FRM_PCI			(DRAM_CH0_BASE_FRM_PCI + CR0_DCSRCOMP_OFF)
#define CR0_DCKRCOMP_FRM_PCI			(DRAM_CH0_BASE_FRM_PCI + CR0_DCKRCOMP_OFF)
#define CR0_DX8X16CKECSCKSEL_FRM_PCI	(DRAM_CH0_BASE_FRM_PCI + CR0_DX8X16CKECSCKSEL_OFF)
#define CR0_RCOMPPRD_FRM_PCI			(DRAM_CH0_BASE_FRM_PCI + CR0_RCOMPPRD_OFF)
#define CR0_DIGFIL_FRM_PCI				(DRAM_CH0_BASE_FRM_PCI + CR0_DIGFIL_OFF)
#define CR0_SLEWPROGRAMMED_FRM_PCI		(DRAM_CH0_BASE_FRM_PCI + CR0_SLEWPROGRAMMED_OFF)
#define CR0_OVRRIDEH_FRM_PCI			(DRAM_CH0_BASE_FRM_PCI + CR0_OVRRIDEH_OFF)
#define CR0_OVRRIDEV_FRM_PCI			(DRAM_CH0_BASE_FRM_PCI + CR0_OVRRIDEV_OFF)
#define CR0_JT_CONFIG_FRM_PCI			(DRAM_CH0_BASE_FRM_PCI + CR0_JT_CONFIG_OFF)

#define PCI_CSR_BASE_FRM_PCI		0xFE000

#define PCI_OUT_INT_MASK_FRM_PCI	(PCI_CSR_BASE_FRM_PCI + PCI_OUT_INT_MASK_OFF)
#define PCI_CONTROL_FRM_PCI			(PCI_CSR_BASE_FRM_PCI + PCI_CONTROL_OFF)
#define PCI_ADDR_EXT_FRM_PCI		(PCI_CSR_BASE_FRM_PCI + PCI_ADDR_EXT_OFF)

#define TB_VENDOR_ID				0x8086
#define TB_DEVICE_ID				0xB154

/* 21154 PCI-to-PCI Bridge register offset */
#define VIDR_OFF					0x0
#define DIDR_OFF					0x2
#define PCR_OFF						0x4
#define PSR_OFF						0x6
#define RIDR_OFF					0x8
#define PIR_OFF						0x9
#define CLSR_OFF					0xC
#define PLTR_OFF					0xD
#define HTR_OFF						0xE
#define PBNR_OFF					0x18
#define SBNR_OFF					0x19
#define SUBBNR_OFF					0x1A
#define SLTR_OFF					0x1B
#define IOBR_OFF					0x1C
#define IOLR_OFF					0x1D
#define SSR_OFF						0x1E
#define MBR_OFF						0x20
#define MLR_OFF						0x22
#define PMBR_OFF					0x24
#define PMLR_OFF					0x26
#define ECPPR_OFF					0x34
#define SUBIDR_OFF					0x36
#define BCR_OFF						0x3E

// 21555 defines
#define NTB_VENDOR_ID               0x8086
#define NTB_DEVICE_ID               0xB555

#define DS_IOMEM_1_TBASE            0x98
#define DS_MEM_2_TBASE              0x9C
#define DS_MEM_3_TBASE              0xA0

// UART defines start 
#define DEFAULT_BAUD	            57600
#define DEFAULT_BAUD_DIVISOR        (50000000 / (16 * DEFAULT_BAUD)) 

#define UART_LineControl           	0x0C     //reg addr
#define UART_DivisorLatchLSB       	0x00	 //reg addr DLAB=0
#define UART_DivisorLatchMSB       	0x04	 //reg addr DLAB=1
#define UART_InterruptEnable      	0x04     //reg addr DLAB=0
#define UART_FIFOControl           	0x08     //reg addr
#define UART_LineStatus           	0x14     //reg addr
#define UART_Transmit             	0        //reg addr
#define IXP2400_UART_ADDR		  	0xC0030000

//end of UART defines

// GPIO defines start
#define GPIO_BASE  0xC0010000
//The are offsets GPIO registers are from GPIO _BASE
#define GPIO_PLR  (GPIO_BASE + 0x00) // GPIO Pin level register
#define GPIO_PDPR	(GPIO_BASE + 0x04) // GPIO Pin direction programmable register
#define GPIO_PDSR	(GPIO_BASE + 0x08) // GPIO Pin direction set register
#define GPIO_PDCR	(GPIO_BASE + 0x0C) // GPIO Pin direction clear register
#define GPIO_POPR	(GPIO_BASE + 0x10) // GPIO Output data programmable register
#define GPIO_POSR	(GPIO_BASE + 0x14) // GPIO Output data set register
#define GPIO_POCR	(GPIO_BASE + 0x18) // GPIO Output data clear register
#define GPIO_REDR	(GPIO_BASE + 0x1C) // GPIO Rising edge detect enable register
#define GPIO_FEDR	(GPIO_BASE + 0x20) // GPIO Falling edge detect enable register
#define GPIO_EDSR	(GPIO_BASE + 0x24) // GPIO Edge detect status register
#define GPIO_LSHR	(GPIO_BASE + 0x28) // GPIO level sensitive high enable register
#define GPIO_LSLR	(GPIO_BASE + 0x2C) // GPIO level sensitive low enable register
#define GPIO_LDSR	(GPIO_BASE + 0x30) // GPIO level detect status register
#define GPIO_INER	(GPIO_BASE + 0x34) // GPIO Interrupt Enable register
#define GPIO_INSR	(GPIO_BASE + 0x38) // GPIO Interrupt Set register
#define GPIO_INCR	(GPIO_BASE + 0x3C) // GPIO Interrupt Reset register
#define GPIO_INST	(GPIO_BASE + 0x40) // GPIO Interrupt Status Register

//end of GPIO defines

#endif /* CYGONCE_HAL_IXDP2400_H */