hal_ixdp2400.h

基于ecos的redboot

#ifndef CYGONCE_HAL_IXDP2400_H
#define CYGONCE_HAL_IXDP2400_H

/* hal_ixdp2400.h
---------------------------------------------------------------------------
                 Copyright (c) 2002, 2003 Intel Corporation
						 All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer. 
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. 
* Neither the name of Intel Corporation nor the names of its contributors
may be used to endorse or promote products derived from this software
without specific prior written permission. 
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                      
---------------------------------------------------------------------------
system: IXDP2400
subsystem: BootMonitor
author: lagarwal
revisions:
--------------------------------------------------------------------------
*/

#define BOOT_THRU_BM				(1 << 31)
#define BOOT_DONT_INIT_PCI			(1 << 30)

#define SLAVE_POST_FLAG_LOC			0xFFFFC
#define POST_DONE					0x12345678

#define SRAM_BASE					0x80000000
#define MIN_SRAM_SIZE				(1024 * 1024) /* 1MB SRAM */
#define MAX_SRAM_SIZE_CSR_VAL		(0xA << 7)
#define SRAM_SIZE_LOOPS				4
#define MAX_QDR_CHANNEL				2

#define SLOW_PORT_BASE				0xC4000000

#define SCRATCHPAD_BASE				0xCA000000

#define CSR_BAR						0
#define SRAM_BAR					1
#define SDRAM_BAR					2

#define CPLD_CSR_BASE				(SLOW_PORT_BASE + 0x3000000)

#define SYSTEM_LED_REG_OFF			0x0
#define ALPHANUM_DIS_DATA_OFF		0x4
#define CPLD_INT_OFF				0xC
#define CPLD_REV_OFF				0x10
#define SYS_CLK_M_OFF				0x14
#define SYS_CLK_N_OFF				0x18

#define SYSTEM_LED					(CPLD_CSR_BASE + SYSTEM_LED_REG_OFF)
#define ALPHANUM_DIS_DATA			(CPLD_CSR_BASE + ALPHANUM_DIS_DATA_OFF)
#define CPLD_INT					(CPLD_CSR_BASE + CPLD_INT_OFF)
#define CPLD_REV					(CPLD_CSR_BASE + CPLD_REV_OFF)
#define SYS_CLK_M					(CPLD_CSR_BASE + SYS_CLK_M_OFF)
#define SYS_CLK_N					(CPLD_CSR_BASE + SYS_CLK_N_OFF)

#define SYSTEM_LED_REG				((volatile cyg_uint32 *)SYSTEM_LED)
#define ALPHANUM_DIS_DATA_REG		((volatile cyg_uint8 *)ALPHANUM_DIS_DATA)
#define CPLD_INT_REG				((volatile cyg_uint8 *)CPLD_INT)
#define CPLD_REV_REG				((volatile cyg_uint32 *)CPLD_REV)
#define SYS_CLK_M_REG				((volatile cyg_uint32 *)SYS_CLK_M)
#define SYS_CLK_N_REG				((volatile cyg_uint32 *)SYS_CLK_N)

// encodings for the 4 char alphanum display
#define DISPLAY_NULL				0x20

#define DIGIT_0						0x0
#define DIGIT_1						0x1
#define DIGIT_2						0x2
#define DIGIT_3						0x3

#define WRITE_TO_CHAR_RAM			0x48
#define DISPLAY_ASCII				0x18

#define USE_8_BIT_DATA				0x1
#define USE_32_BIT_DATA				0x0

#define WR_HD						0x1
#define WR_PW						0x2
#define WR_SU						0x0
#define SP_WTC1_VAL					(WR_SU << 6 | WR_PW << 2 | WR_HD)

#define NO_BOOT_ROM					0x0
#define CFG_PCI_BOOT_HOST			(1 << 2)
#define CFG_PROM_BOOT				(1 << 1)

#define IXP2400_VENDOR_ID			0x8086
#define IXP2400_DEVICE_ID			0x9001

#define INIT_COMP					(1 << 21)
#define RSTALL						(1 << 16)
#define DRAM_RST                    (1 << 11)
#define PCIRST						(1 << 2)
#define RESET_PCI					(1 << 1)
#define RESET_XSCALE				(1 << 0)
#define NOT_RESET_PCI				~(PCIRST | RESET_PCI)

#define PCI_CONTROL_BE_DEO			(1 << 22) /* PCI Big Endian Data Enable Out */
#define PCI_CONTROL_BE_DEI			(1 << 21) /* PCI Big Endian Data Enable In */
#define PCI_CONTROL_BE_BEO			(1 << 20) /* PCI Big Endian Byte Enable Out */
#define PCI_CONTROL_BE_BEI			(1 << 19) /* PCI Big Endian Byte Enable In */

#define CCR_200MHZ_DIVISOR			0x3
#define CCR_150MHZ_DIVISOR			0x4
#define CCR_100MHZ_DIVISOR			0x6

#define PIPELINE					(1 << 10)
#define PARITY_ENABLE				(1 << 3)

#define FLASH_WRITE_ENABLE			(1 << 9)
#define FLASH_ALIAS_DISABLE			(1 << 8)

#define DDR_RX_DLL_VAL				0x11
#define DDR_RX_DESKEW_VAL			0x11
#define DDR_RDDLYSEL_RECEN_VAL		0x11
#define DDR_RCOMP_IO_CONFIG_VAL		0x0

#define TRP							0
#define TRCD						(0 << 1)
#define RD_RD_SPACING				(0 << 8)
#define RD_WR_SPACING				(0 << 9)
#define TWTR						(0 << 10)
#define REF_EN						(1 << 14)
#define TWR							(0 << 27)
#define TRFC						(0 << 29)
#define DU_CONTROL_FIXED_VAL		(TRFC | TWR | REF_EN | TWTR | RD_WR_SPACING | RD_RD_SPACING | TRCD | TRP)

#define RESET_DLL					0x100
#define LOAD_MODE_NORMAL			0x62
#define PRECHARGE_ALL				(1 << 10)
#define EXT_LD_MODE					(1 << 12)
#define SIDE0						(1 << 14)
#define SIDE1						(1 << 15)
#define CKE							(1 << 16)
#define PRECHARGE					(1 << 29)
#define REFRESH						(1 << 30)
#define LD_MODE_REG					(1 << 31)

#define DISABLE_CHK					(1 << 8)

#define SOFT_INT					(1 << 0)
#define ERROR_SUM					(1 << 1)
#define UART_INT					(1 << 2)
#define GPIO_INT					(1 << 3)
#define TIMER_UFLOW					(0xF << 4)
#define SP_INT						(1 << 8)
#define PCI_DOORBELL				(1 << 13)

#define IRQ_ENABLE_SET_VAL			(PCI_DOORBELL | SP_INT | TIMER_UFLOW | GPIO_INT | UART_INT | ERROR_SUM | SOFT_INT)

#define PCIIM						(1 << 25)
#define PILM						(3 << 26)

#define XSCALE_INT_ENABLE_VAL		(PILM | PCIIM)

#define ACTIVATE_TIMER				(1 << 7)

#define T1_CTL_VAL					ACTIVATE_TIMER

#define CLEAR_INT					1

#define T1_CLR_VAL					CLEAR_INT

#define IO_SPACE_ENABLE				(1 << 0)
#define MEM_SPACE_ENABLE			(1 << 1)
#define BUS_MASTER_ENABLE			(1 << 2)
#define WR_INV_ENABLE				(1 << 4)

#define PCI_CMD_STAT_VAL			(WR_INV_ENABLE | BUS_MASTER_ENABLE | MEM_SPACE_ENABLE | IO_SPACE_ENABLE)

#define XSIM						~(1 << 1)

/* Global control registers */
#define GLOBAL_CONTROL_BASE			0xC0004A00

#define PRODUCT_ID_OFF              0x0
#define MISC_CONTROL_OFF			0x4
#define IXP_RESET0_OFF				0xC
#define CCR_OFF						0x14
#define STRAP_OPTIONS_OFF			0x18

#define PRODUCT_ID				    (GLOBAL_CONTROL_BASE + PRODUCT_ID_OFF)
#define MISC_CONTROL				(GLOBAL_CONTROL_BASE + MISC_CONTROL_OFF)
#define IXP_RESET0					(GLOBAL_CONTROL_BASE + IXP_RESET0_OFF)
#define CCR							(GLOBAL_CONTROL_BASE + CCR_OFF)
#define STRAP_OPTIONS				(GLOBAL_CONTROL_BASE + STRAP_OPTIONS_OFF)

#define PRODUCT_ID_REG			    ((volatile cyg_uint32 *)PRODUCT_ID)
#define MISC_CONTROL_REG			((volatile cyg_uint32 *)MISC_CONTROL)
#define IXP_RESET0_REG				((volatile cyg_uint32 *)IXP_RESET0)
#define CCR_REG						((volatile cyg_uint32 *)CCR)
#define STRAP_OPTIONS_REG			((volatile cyg_uint32 *)STRAP_OPTIONS)

/* Timer registers */
#define TIMER_CSR_BASE				0xC0020000

#define T1_CTL_OFF					0x0
#define T1_CLD_OFF					0x10
#define T1_CSR_OFF					0x20
#define T1_CLR_OFF					0x30

#define T1_CTL_REG					((volatile cyg_uint32 *)(TIMER_CSR_BASE + T1_CTL_OFF))
#define T1_CLD_REG					((volatile cyg_uint32 *)(TIMER_CSR_BASE + T1_CLD_OFF))
#define T1_CSR_REG					((volatile cyg_uint32 *)(TIMER_CSR_BASE + T1_CSR_OFF))
#define T1_CLR_REG					((volatile cyg_uint32 *)(TIMER_CSR_BASE + T1_CLR_OFF))

/* slowport registers */
#define SLOWPORT_REGISTER_BASE		0xC0080000

#define SP_CCR_OFF					0x0
#define SP_WTC1_OFF					0x4
#define SP_WTC2_OFF					0x8
#define SP_RTC1_OFF					0xC
#define SP_RTC2_OFF					0x10
#define SP_FAC_OFF					0x20
#define SP_FRM_OFF					0x24

#define SP_CCR						(SLOWPORT_REGISTER_BASE + SP_CCR_OFF)
#define SP_WTC1						(SLOWPORT_REGISTER_BASE + SP_WTC1_OFF)
#define SP_WTC2						(SLOWPORT_REGISTER_BASE + SP_WTC2_OFF)
#define SP_RTC1						(SLOWPORT_REGISTER_BASE + SP_RTC1_OFF)
#define SP_RTC2						(SLOWPORT_REGISTER_BASE + SP_RTC2_OFF)
#define SP_FAC						(SLOWPORT_REGISTER_BASE + SP_FAC_OFF)
#define SP_FRM						(SLOWPORT_REGISTER_BASE + SP_FRM_OFF)

#define SP_CCR_REG					((volatile cyg_uint32 *)SP_CCR)
#define SP_WTC1_REG					((volatile cyg_uint32 *)SP_WTC1)
#define SP_WTC2_REG					((volatile cyg_uint32 *)SP_WTC2)
#define SP_RTC1_REG					((volatile cyg_uint32 *)SP_RTC1)
#define SP_RTC2_REG					((volatile cyg_uint32 *)SP_RTC2)
#define SP_FAC_REG					((volatile cyg_uint32 *)SP_FAC)
#define SP_FRM_REG					((volatile cyg_uint32 *)SP_FRM)

/* sram registers */
#define QDR_CH_CSR_BASE				0xCC010000

#define QDR_CH_CONTROL_OFF			0x0
#define QDR_RX_DLL_OFF				0x228
#define QDR_RD_PTR_OFF				0x240
#define QDR_RX_DESKEW_OFF			0x244