hal_platform_setup.h

基于ecos的redboot

	str	r1, [r0]

	/* Program DDR DQ/DQS pull-up and pull-down Slew Lookup table registers */
	/* (cr0_ddqpslew0 - cr0_ddqpslew3) and (cr0_ddqnslew0 - cr0_ddqnslew3) */

	ldr r1, =0xcccccccc

	ldr r0, =0xd0000150
	ldr r2, =0xd0000188
DQ_DQS:
	str	r1, [r0]
	add r0, r0, #0x8
	cmp r0, r2
	ble DQ_DQS

	/* Program MA/BA/RAS#/CAS#/WE# pull-up and pull-down Slew Lookup table registers */
	/* (cr0_dctlpslew0 - cr0_dctlpslew3) and (cr0_dctlnslew0 - cr0_dctlnslew3) */
	ldr r0, =0xd0000198
	ldr r2, =0xd00001D0
MA_BA_RAS_CAS_WE:
	str	r1, [r0]
	add r0, r0, #0x8
	cmp r0, r2
	ble MA_BA_RAS_CAS_WE

	/* Program RCV pull-up and pull-down Slew Lookup table registers */
	/* (cr0_drcvpslew0 - cr0_drcvpslew3) and (cr0_drcvnslew0 - cr0_drcvnslew3) */
	ldr r0, =0xd00001E0
	ldr r2, =0xd0000218
RCV:
	str	r1, [r0]
	add r0, r0, #0x8
	cmp r0, r2
	ble RCV

	/* Program CKE x8 pull-up and pull-down Slew Lookup table registers */
	/* (cr0_dckex8pslew0 - cr0_dckex8pslew3) and (cr0_dckex8nslew0 - cr0_dckex8nslew3) */
	ldr r0, =0xd0000230
	ldr r2, =0xd0000268
CKE_x8:
	str	r1, [r0]
	add r0, r0, #0x8
	cmp r0, r2
	ble CKE_x8

	/* Program CKE x16 pull-up and pull-down Slew Lookup table registers */
	/* (cr0_dckex16pslew0 - cr0_dckex16pslew3) and (cr0_dckex16nslew0 - cr0_dckex16nslew3) */
	ldr r0, =0xd0000270
	ldr r2, =0xd00002A8
CKE_x16:
	str	r1, [r0]
	add r0, r0, #0x8
	cmp r0, r2
	ble CKE_x16

	/* Program CS# x8 pull-up and pull-down Slew Lookup table registers */
	/* (cr0_dcsx8pslew0 - cr0_dcsx8pslew3) and (cr0_dcsx8nslew0 - cr0_dcsx8nslew3) */
	ldr r0, =0xd00002B8
	ldr r2, =0xd00002F0
CS_x8:
	str	r1, [r0]
	add r0, r0, #0x8
	cmp r0, r2
	ble CS_x8

	/* Program CS# x16 pull-up and pull-down Slew Lookup table registers */
	/* (cr0_dcsx16pslew0 - cr0_dcsx16pslew3) and (cr0_dcsx16nslew0 - cr0_dcsx16nslew3) */
	ldr r0, =0xd00002F8
	ldr r2, =0xd0000330
CS_x16:
	str	r1, [r0]
	add r0, r0, #0x8
	cmp r0, r2
	ble CS_x16

	/* Program CK CK# x8 pull-up and pull-down Slew Lookup table registers */
	/* (cr0_dckx8pslew0 - cr0_dckx8pslew3) and (cr0_dckx8nslew0 - cr0_dckx8nslew3) */
	ldr r0, =0xd0000340
	ldr r2, =0xd0000378
CK_x8:
	str	r1, [r0]
	add r0, r0, #0x8
	cmp r0, r2
	ble CK_x8

	/* Program CK CK# x16 pull-up and pull-down Slew Lookup table registers */
	/* (cr0_dckx16pslew0 - cr0_dckx16pslew3) and (cr0_dckx16nslew0 - cr0_dckx16nslew3) */
	ldr r0, =0xd0000380
	ldr r2, =0xd00003B8

CK_x16:
	str	r1, [r0]
	add r0, r0, #0x8
	cmp r0, r2
	ble CK_x16

    /* Flag Slew Programmed register as done */
	ldr r0, =CR0_SLEWPROGRAMMED
	ldr r1, =0x00000001
	str	r1, [r0]

    /* cr0_ovrrideh: turn off h override, 0x0 */
	
	ldr r1, =0x00000000

	ldr r0, =CR0_OVRRIDEH	
	str	r1, [r0]

    /* cr0_ovrridev: turn off v override, 0x0 */
	ldr r0, =CR0_OVRRIDEV
	str	r1, [r0]

    /* De-Select Test Mode (cr0_jt_config) at address offset 0x3C0 
       User Overide RCOMP settings */
	ldr r0, =CR0_JT_CONFIG
	str	r1, [r0]

	// wait for 2000 cycles
	mov r0, #0x0
wait_ddr_io:
	add r0, r0, #1
	cmp r0, #2000
	bne wait_ddr_io

	HEX_DISPLAY 'D', 'D', 'R', 'I'

	// load the fixed parmeters
	ldr r3, =DU_CONTROL_FIXED_VAL
	// now read DDR SPD and determine the right value for DU_CONTROL

	// first determine lowest possible CAS latency
	// DDR is running @ 150 MHZ ~ 6.6 ns
	// so first look at CL = 2 if its <= 6.6 otherwise set CL = 2.5
	//I2C_INIT0
	mov r4, #(2 << 2)
	I2C_READ 0xa0, 23, r5
	cmp r5, #0x60
	ble tcl_set
	// else set CL = 2.5
	mov r4, #(1 << 2)
tcl_set:
	orr r3, r3, r4

	// now set TRAS
	I2C_READ 0xa0, 30, r5
	// check for 5 dram clock
	mov r4, #(2 << 4)
	cmp r5, #33
	ble tras_set
	// check for 6 dram clock
	mov r4, #(1 << 4)
	cmp r5, #39
	ble tras_set
	// set 7 dram clock
	mov r4, #(0 << 4)
tras_set:
	orr r3, r3, r4

	// set TRC
	I2C_READ 0xa0, 41, r5
#if 0
	mov r4, #(3 << 6)
	cmp r5, #46
	ble trc_set
	// check for 8 dram clock
	mov r4, #(2 << 6)
	cmp r5, #53
	ble trc_set
#endif
	// check for 9 dram clock
	mov r4, #(1 << 6)
	cmp r5, #60
	ble trc_set
	// set 10 dram clock
	mov r4, #(0 << 6)
trc_set:
	orr r3, r3, r4

	// next DIMM sides and refresh counter
	I2C_READ 0xa0, 5, r5
	// check for one side
	cmp r5, #1
	// nothing to set -> jump to set refresh rate
	beq one_side
	// else 2 sides
	mov r4, #(1 << 26)
	orr r3, r3, r4
	// refresh rate for 2 sides
	I2C_READ 0xa0, 12, r5
	// check for 7.8 us
	mov r4, #(12 << 15)
	// check if running @ 100 MHz
	ldr	r0, =CCR
	ldr	r1, [r0]
	mov r1, r1, LSR #16
	cmp r1, #6
	bge chk_double_side_7_8_comp
	mov r4, #(18 << 15)
chk_double_side_7_8_comp:
	cmp r5, #0x82
	beq ref_rate_set
	// else 15.6 us
	mov r4, #(24 << 15)
	// check if running @ 100 MHz
	ldr	r0, =CCR
	ldr	r1, [r0]
	mov r1, r1, LSR #16
	cmp r1, #6
	bge chk_double_side_15_6_comp
	mov r4, #(36 << 15)
chk_double_side_15_6_comp:
	b ref_rate_set
	// refresh rate for 1 side
one_side:
	I2C_READ 0xa0, 12, r5
	// check for 7.8 us
	mov r4, #(24 << 15)
	// check if running @ 100 MHz
	ldr	r0, =CCR
	ldr	r1, [r0]
	mov r1, r1, LSR #16
	cmp r1, #6
	bge chk_one_side_7_8_comp
	mov r4, #(36 << 15)
chk_one_side_7_8_comp:
	cmp r5, #0x82
	beq ref_rate_set
	// else 15.6 us
	mov r4, #(48 << 15)
	// check if running @ 100 MHz
	ldr	r0, =CCR
	ldr	r1, [r0]
	mov r1, r1, LSR #16
	cmp r1, #6
	bge ref_rate_set
	mov r4, #(73 << 15)
ref_rate_set:
	orr r3, r3, r4

	// number of row and column
	I2C_READ 0xa0, 3, r5
	I2C_READ 0xa0, 4, r6
	add r6, r5, r6
	add r6, r6, #2
	// check for 8 Mbit part
	cmp r6, #23
	bne not_8_mbit_part
	mov r4, #(0 << 23)
	b num_row_col_set
not_8_mbit_part:
	// check for 16 Mbit part
	cmp r6, #24
	bne not_16_mbit_part
	I2C_READ 0xa0, 13, r8
	// check for x8 part
	cmp r8, #8
	bne part_16mbit_x16
	mov r4, #(1 << 23)
	b num_row_col_set
part_16mbit_x16:
	mov r4, #(2 << 23)
	b num_row_col_set
not_16_mbit_part:
	// check for 32 Mbit part
	cmp r6, #25
	bne not_32_mbit_part
	mov r4, #(3 << 23)
	b num_row_col_set
not_32_mbit_part:
	// check for 64 Mbit part
	cmp r6, #26
	bne part_128_mbit
	I2C_READ 0xa0, 13, r6
	// check for x8 part
	cmp r6, #8
	bne part_64mbit_x16
	mov r4, #(4 << 23)
	b num_row_col_set
part_64mbit_x16:
	mov r4, #(5 << 23)
	b num_row_col_set
part_128_mbit:
	// it has to be 128 Mbit part
	mov r4, #(6 << 23)
num_row_col_set:
	orr r3, r3, r4

	// now set TRRD
	I2C_READ 0xa0, 28, r5
	// check for 2 dram clock
	mov r4, #(1 << 28)
	cmp r5, #0x30
	ble trrd_set
	// set 3 dram clock
	mov r4, #(0 << 28)
trrd_set:
	orr r3, r3, r4

	//set du_control
	ldr	r0, =DU_CONTROL
	str	r3, [r0]

	// enable clock
	ldr	r0, =DU_INIT
	ldr	r1, =CKE
	str	r1, [r0]

	// precharge all
	ldr	r0, =DU_INIT
	ldr	r1, =(PRECHARGE | SIDE1 | SIDE0 | PRECHARGE_ALL)
	str	r1, [r0]
wait_precharge1:
	ldr r0, =DU_INIT
	ldr r1, [r0]
	tst	r1, #PRECHARGE
	bne wait_precharge1

	// issue EMRS to enable DLL
	ldr	r0, =DU_INIT
	ldr	r1, =(LD_MODE_REG | SIDE1 | SIDE0 | EXT_LD_MODE)
	str	r1, [r0]
wait_enable:
	ldr r0, =DU_INIT
	ldr r1, [r0]
	tst	r1, #LD_MODE_REG
	bne wait_enable

	// Reset DLL
	ldr	r0, =DU_INIT
	ldr	r1, =(LD_MODE_REG | SIDE1 | SIDE0 | RESET_DLL)
	str	r1, [r0]
wait_reset:
	ldr r0, =DU_INIT
	ldr r1, [r0]
	tst	r1, #LD_MODE_REG
	bne wait_reset

	// precharge all
	ldr	r0, =DU_INIT
	ldr	r1, =(PRECHARGE | SIDE1 | SIDE0 | PRECHARGE_ALL)
	str	r1, [r0]
wait_precharge2:
	ldr r0, =DU_INIT
	ldr r1, [r0]
	tst	r1, #PRECHARGE
	bne wait_precharge2

	// issue 2 auto refresh commands
	ldr	r0, =DU_INIT
	ldr	r1, =(REFRESH | SIDE1 | SIDE0)
	str	r1, [r0]
wait_refresh1:
	// wait till auto refresh is done
	ldr r0, =DU_INIT
	ldr r1, [r0]
	tst	r1, #REFRESH
	bne wait_refresh1

	ldr	r0, =DU_INIT
	ldr	r1, =(REFRESH | SIDE1 | SIDE0)
	str	r1, [r0]
wait_refresh2:
	// wait till auto refresh is done
	ldr r0, =DU_INIT
	ldr r1, [r0]
	tst	r1, #REFRESH
	bne wait_refresh2

	// init device operation
	// settings - burst length = 4, burst type - sequential, CAS latency = 2.5
	ldr	r0, =DU_INIT
	ldr	r1, =(LD_MODE_REG | SIDE1 | SIDE0 | LOAD_MODE_NORMAL)
	str	r1, [r0]
wait_start:
	ldr r0, =DU_INIT
	ldr r1, [r0]
	tst	r1, #LD_MODE_REG
	bne wait_start

	// disable ecc so that it doesn't generate ecc errors.
	// even if you disable ecc ecc will be calculated and stored
	ldr r0, =DU_ECC_TEST		// load the register address in r0        
    ldr r1, [r0]				// read the reg contnets into r1
    orr r1, r1, #DISABLE_CHK	// set the disable bit
    str r1, [r0]				// write the value to the register

	// here is what I am doing here.
	// flash is aliased at 0 so I am trying to start executing from real flash
	// addr. so that when I unalias flash I still have the right value in pc.
	ldr	r2, =flash_real_addr
	ldr	r3, =SLOW_PORT_BASE
	add r2, r3, r2
	mov pc, r2

flash_real_addr:
	ldr	r0, =MISC_CONTROL				// Load the address of the misc control Register in r0
	ldr	r1, [r0]						// store old value in r1
	ldr r2, =FLASH_ALIAS_DISABLE
	orr r1, r1, r2						// disable flash aliasing
	str	r1, [r0]						// Store to misc control Register

do_post:
    HEX_DISPLAY 'P', 'O', 'S', 'T'
	POST

	cmp r10, #0
	// On slave if flash is not present then jump to scrubbing
	beq scrub_set

    HEX_DISPLAY 'C', 'O', 'P', 'Y'
	ROMRAM_COPY

	ldr	r11, =(CYGMEM_REGION_ram + CYGMEM_REGION_rom_SIZE)
	b scrub_mem

scrub_set:
	// Master scrubs first 1M of slave
	ldr	r11, =(CYGMEM_REGION_ram + 0x100000)
	
scrub_mem:
    HEX_DISPLAY DISPLAY_NULL, 'M', 'M', 'U'
    // Enable access to all coprocessor registers
	ldr	r0, =0x2001			// enable access to all coprocessors
	mcr	p15, 0, r0, c15, c1, 0
	
	mcr	p15, 0, r0, c7, c10, 4		// drain the write & fill buffers
	CPWAIT r0	
	
	mcr	p15, 0, r0, c7, c7, 0		// flush Icache, Dcache and BTB
	CPWAIT r0	
	
	mcr	p15, 0, r0, c8, c7, 0		// flush instuction and data TLBs
	CPWAIT r0	
	
	// Enable the Icache
	mrc	p15, 0, r0, c1, c0, 0
	orr	r0, r0, #MMU_Control_I
	mcr	p15, 0, r0, c1, c0, 0
	CPWAIT  r0

	// Set the TTB register
	ldr	r0, =0x4000
	mcr	p15, 0, r0, c2, c0, 0

	// Enable permission checks in all domains
	ldr	r0, =0x55555555
	mcr	p15, 0, r0, c3, c0, 0
	
	// Enable the MMU
	mrc	p15, 0, r0, c1, c0, 0
	orr	r0, r0, #MMU_Control_M
	orr	r0, r0, #MMU_Control_R
	mcr	p15, 0, r0, c1, c0, 0
	CPWAIT  r0
	
	mcr	p15, 0, r0, c7, c10, 4		// drain the write & fill buffers
	CPWAIT r0	
	
	// Enable the Dcache
	mrc	p15, 0, r0, c1, c0, 0
	orr	r0, r0, #MMU_Control_C
	mcr	p15, 0, r0, c1, c0, 0
	CPWAIT  r0

    // Initialize branch target buffer
    BTB_INIT r0

    HEX_DISPLAY 'S', 'C', 'R', 'B'
	// scrub/init SDRAM
	mov	r0, #0				// scrub with 0x0000:0000
	mov	r1, #0
	mov	r2, #0	
	mov	r3, #0
	mov	r4, #0
	mov	r5, #0
	mov	r6, #0
	mov	r7, #0

10: // fastScrubLoop
	stmia r11!, {r0-r7}
	cmp r11, r8
	beq	15f
	b 10b

15:
	ldr	r0, =SLAVE_POST_FLAG_LOC
	ldr	r1, =POST_DONE
	str	r1, [r0]

	ldr r0, =DU_ECC_TEST		// Load the register addr into r0
    ldr r1, [r0]			    // load the register contents into r1
    bic r1, r1, #DISABLE_CHK	// clear the DISABLE_CHK bit
    str r1, [r0]				// write it back to the register

	// Save SDRAM size
    ldr     r1, =hal_dram_size
	str	r8, [r1]
	.endm    // _platform_setup1

/*---------------------------------------------------------------------------*/
/* end of hal_platform_setup.h                                               */
#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */