📄 hal_platform_setup.h
字号:
#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
#define CYGONCE_HAL_PLATFORM_SETUP_H
/* hal_platform_setup.h
---------------------------------------------------------------------------
Copyright (c) 2002, 2003 Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors
may be used to endorse or promote products derived from this software
without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------
system: IXDP2400
subsystem: BootMonitor
author: lagarwal
revisions:
--------------------------------------------------------------------------
*/
#include <pkgconf/system.h> // System-wide configuration info
#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
#include CYGHWR_MEMORY_LAYOUT_H // Location of the ROM
#include <cyg/hal/hal_ixdp2400.h> // Platform specific hardware definitions
#include <cyg/hal/hal_mmu.h> // MMU definitions
#include <cyg/hal/post.h>
#define MMU_Control_BTB 0x800
// Define macro used to diddle the LEDs during early initialization.
// Can use r0+r1. Argument in \x.
#ifdef __ARMEB__
#define CYGHWR_LED_MACRO \
b 667f ;\
666: ;\
.byte 0x30, 0x31, 0x32, 0x33 ;\
.byte 0x34, 0x35, 0x36, 0x37 ;\
.byte 0x38, 0x39, 0x41, 0x42 ;\
.byte 0x43, 0x44, 0x45, 0x46 ;\
667: ;\
ldr r0, =PRODUCT_ID ;\
ldr r1, [r0] ;\
and r1, r1, #0xF0 ;\
cmp r1, #0 ;\
beq 668f ;\
ldr r0, =666b ;\
add r0, r0, #\x ;\
ldrb r2, [r0] ;\
ldr r0, =ALPHANUM_DIS_DATA ;\
strb r2, [r0] ;\
add r0, r0, #1 ;\
ldrb r1, ='0' ;\
strb r1, [r0] ;\
add r0, r0, #1 ;\
strb r1, [r0] ;\
add r0, r0, #1 ;\
strb r1, [r0] ;\
b 669f ;\
668: ;\
ldr r0, =666b ;\
add r0, r0, #\x ;\
ldrb r2, [r0] ;\
ldr r0, =ALPHANUM_DIS_DATA ;\
ldrb r1, ='0' ;\
strb r1, [r0] ;\
add r0, r0, #1 ;\
strb r1, [r0] ;\
add r0, r0, #1 ;\
strb r1, [r0] ;\
add r0, r0, #1 ;\
strb r2, [r0] ;\
669:
#else
#define CYGHWR_LED_MACRO \
b 667f ;\
666: ;\
.byte 0x30, 0x31, 0x32, 0x33 ;\
.byte 0x34, 0x35, 0x36, 0x37 ;\
.byte 0x38, 0x39, 0x41, 0x42 ;\
.byte 0x43, 0x44, 0x45, 0x46 ;\
667: ;\
ldr r0, =666b ;\
add r0, r0, #\x ;\
ldrb r2, [r0] ;\
ldr r0, =ALPHANUM_DIS_DATA ;\
strb r2, [r0] ;\
add r0, r0, #1 ;\
ldrb r1, ='0' ;\
strb r1, [r0] ;\
add r0, r0, #1 ;\
strb r1, [r0] ;\
add r0, r0, #1 ;\
strb r1, [r0]
#endif
// If we are doing a ROMRAM startup copy all sections up to the start of
// the data section to RAM.
#if defined(CYG_HAL_STARTUP_ROMRAM)
#define ROMRAM_COPY \
ldr r0, =(CYGMEM_REGION_rom) ;\
ldr r1, =0 ;\
ldr r2, =(CYGMEM_REGION_rom_SIZE) ;\
copy_loop: ;\
ldr r3, [r0], #4 ;\
str r3, [r1], #4 ;\
cmp r1, r2 ;\
bne copy_loop ;\
ldr r0, =830f ;\
mov pc, r0 ;\
830:
#else
#define ROMRAM_COPY
#endif
#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
#define PLATFORM_SETUP1 _platform_setup1
#else
#define PLATFORM_SETUP1
#endif
// Display all the 4 chars.
.macro HEX_DISPLAY char4, char3, char2, char1
#ifdef __ARMEB__
ldr r0, =PRODUCT_ID
ldr r1, [r0]
and r1, r1, #0xF0
ldr r0, =ALPHANUM_DIS_DATA
cmp r1, #0
// branch if A step
beq 670f
// else B step
ldrb r1, =\char1
strb r1, [r0]
add r0, r0, #1
ldrb r1, =\char2
strb r1, [r0]
add r0, r0, #1
ldrb r1, =\char3
strb r1, [r0]
add r0, r0, #1
ldrb r1, =\char4
strb r1, [r0]
b 671f
670:
ldrb r1, =\char4
strb r1, [r0]
add r0, r0, #1
ldrb r1, =\char3
strb r1, [r0]
add r0, r0, #1
ldrb r1, =\char2
strb r1, [r0]
add r0, r0, #1
ldrb r1, =\char1
strb r1, [r0]
671:
#else
ldr r0, =ALPHANUM_DIS_DATA
ldrb r1, =\char1
strb r1, [r0]
add r0, r0, #1
ldrb r1, =\char2
strb r1, [r0]
add r0, r0, #1
ldrb r1, =\char3
strb r1, [r0]
add r0, r0, #1
ldrb r1, =\char4
strb r1, [r0]
#endif
.endm
// wait for coprocessor write complete
.macro CPWAIT reg
mrc p15,0,\reg,c2,c0,0
mov \reg,\reg
sub pc,pc,#4
.endm
// Enable the BTB
.macro BTB_INIT reg
mrc p15, 0, \reg, c1, c0, 0
orr \reg, \reg, #MMU_Control_BTB
mcr p15, 0, \reg, c1, c0, 0
CPWAIT \reg
.endm
// form a first-level section entry
.macro FL_SECTION_ENTRY base,x,ap,p,d,c,b
.word (\base << 20) | (\x << 12) | (\ap << 10) | (\p << 9) |\
(\d << 5) | (\c << 3) | (\b << 2) | 2
.endm
// form a first-level page table entry
.macro FL_PT_ENTRY base,p,d
// I wanted to use logical operations here, but since I am using symbols later
// to fill in the parameters, I had to use addition to force the assembler to
// do it right
.word \base + (\p << 9) + (\d << 5) + 1
.endm
// form a second level small page entry
.macro SL_SMPAGE_ENTRY base,ap3,ap2,ap1,ap0,c,b
.word (\base << 12) | (\ap3 << 10) | (\ap2 << 8) | (\ap1 << 6) |\
(\ap0 << 4) | (\c << 3) | (\b << 2) | 2
.endm
// form a second level extended small page entry
.macro SL_XSMPAGE_ENTRY base,x,ap,c,b
.word (\base << 12) | (\x << 6) | (\ap << 4) | (\c << 3) | (\b << 2) | 3
.endm
// start of platform setup
.macro _platform_setup1
// This is where we wind up immediately after reset.
// since we need to align the mmu table on a 16k boundary, we just branch around the page
// table which we will locate at FLASH_BASE+0x4000.
b _real_platform_setup
.p2align 13
// the following alignment creates the mmu table at address 0x4000.
mmu_table:
.set __base,0
// map cacheable SDRAM
.rept UNCACHED_SDRAM_START
FL_SECTION_ENTRY __base,0,3,0,0,1,1
.set __base,__base+1
.endr
// map non-cached SDRAM
.rept UNCACHED_SDRAM_SZ
FL_SECTION_ENTRY __base,1,3,0,0,0,1
.set __base,__base+1
.endr
// Make rest of SDRAM rw, cacheable and bufferable
.rept 0x800 - (UNCACHED_SDRAM_START + UNCACHED_SDRAM_SZ)
FL_SECTION_ENTRY __base,0,3,0,0,1,1
.set __base,__base+1
.endr
// map sram
.rept 0xC00 - 0x800
FL_SECTION_ENTRY __base,0,3,0,0,1,1
.set __base,__base+1
.endr
// Make CSR, flash and PCI Mem as rw, non-cacheable and non-bufferable
.rept 0x1000 - 0xC00
FL_SECTION_ENTRY __base,1,3,0,0,0,1
.set __base,__base+1
.endr
_real_platform_setup:
#ifdef __ARMEB__
// switch to big endian mode first thing so that we don't have to mess with constants
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #0x80
mcr p15, 0, r0, c1, c0, 0
CPWAIT r0
#endif
ldr r0, =STRAP_OPTIONS // Load the address of the strap options Register in r0
ldr r1, [r0] // get value in r1
and r10, r1, #CFG_PROM_BOOT // save single/dual boot rom in r10
and r9, r1, #CFG_PCI_BOOT_HOST
// read the value of RTC1 and put it in WTC1, RTC2, WTC2 register
ldr r0, =SP_RTC1
ldr r1, [r0]
ldr r0, =SP_WTC1 // Load the address of the slow port write timing control 1 Register in r0
str r1, [r0] // Store to slow port write timing control Register
ldr r0, =SP_WTC2 // Load the address of the slow port write timing control 2 Register in r0
str r1, [r0] // Store to slow port write timing control 2 Register
ldr r0, =SP_RTC2 // Load the address of the slow port read timing control 2 Register in r0
str r1, [r0] // Store to slow port read timing control 2 Register
ldr r0, =MISC_CONTROL // Load the address of the misc control Register in r0
ldr r1, [r0] // store old value in r1
ldr r2, =FLASH_WRITE_ENABLE
orr r1, r1, r2 // make flash write enable for flash utility
str r1, [r0] // Store to misc control Register
HEX_DISPLAY DISPLAY_NULL, 'P', 'C', 'I'
cmp r10, #0
// On slave if flash is not present then I am doing all the init. from master so skip everything
beq do_post
// take pci out of reset
// I am taking PCI out of reset here and not in cyg_hal_plf_pci_init function so that in dual flash mode
// slave can set init_comp bit as soon as possible
ldr r0, =IXP_RESET0
ldr r1, [r0]
bic r1, r1, #PCIRST
bic r1, r1, #RESET_PCI
str r1, [r0]
HEX_DISPLAY 'P', 'C', 'I', 'C'
// 8 dummy writes to flush pci cmd fifo
mov r3, #0x0
ldr r0, =MAILBOX_0
ldr r1, =0x0
pci_cmd_fifo_flush_loop:
str r1, [r0]
add r3, r3, #1
cmp r3, #8
bne pci_cmd_fifo_flush_loop
#ifdef A0_REV
HEX_DISPLAY 'P', 'C', 'I', 'R'
// set PCI rcomp registers
ldr r0, =PCI_RCOMP_OVER
ldr r1, =0x153239
str r1, [r0]
#endif
cmp r9, #0
// On slave skip setting pci rcomp register
beq ddr_rcomp_set
#ifdef A0_REV
// I have to write slave's pci rcomp register within 2000 cycles.
ldr r0, =0xDA200060
ldr r1, =0x153239
str r1, [r0]
#endif
HEX_DISPLAY 'D', 'D', 'R', 'R'
ddr_rcomp_set:
// now DRAM rcomp IO config registers
ldr r0, =DDR_RCOMP_IO_CONFIG
ldr r1, =DDR_RCOMP_IO_CONFIG_VAL
str r1, [r0]
#ifdef A0_REV
ldr r0, =SYS_CLK_M
ldr r1, [r0]
and r1, r1, #0xFF
ldr r4, =CCR_150MHZ_DIVISOR
cmp r1, #0x55
bne sram_divisor_set
ldr r4, =CCR_200MHZ_DIVISOR
#else
I2C_INIT0
cmp r9, #0
// On master skip reading QDR channel 0 I2C PROM
bne set_sram_200mhz
// read the data
I2C_READ 0xa8, 0x50, r3
mov r3, r3, LSL #24
I2C_READ 0xa8, 0x51, r5
mov r5, r5, LSL #16
orr r3, r3, r5
I2C_READ 0xa8, 0x52, r5
mov r5, r5, LSL #8
orr r3, r3, r5
I2C_READ 0xa8, 0x53, r5
orr r3, r3, r5
cmp r3, #100
bne sram_not_100mhz
ldr r4, =CCR_100MHZ_DIVISOR
b sram_divisor_set
sram_not_100mhz:
cmp r3, #150
bne set_sram_200mhz
ldr r4, =CCR_150MHZ_DIVISOR
b sram_divisor_set
set_sram_200mhz:
ldr r4, =CCR_200MHZ_DIVISOR
#endif
// reset DDR and take it out of reset to prevent DLL latch at 100 MHZ
ldr r0, =IXP_RESET0
ldr r1, =DRAM_RST
str r1, [r0]
ldr r0, =IXP_RESET0
ldr r1, [r0]
bic r1, r1, #DRAM_RST
str r1, [r0]
sram_divisor_set:
HEX_DISPLAY 'C', 'L', 'K', 'I'
// now set the operating freq. for SRAM/SDRAM interface
mov r3, #0x0
orr r3, r3, #(CCR_200MHZ_DIVISOR << 4) // Set SRAM channel 1 clock ratio
orr r3, r3, r4 // Set SRAM channel 0 clock ratio
// now set DDR clock
//I2C_INIT0
I2C_READ 0xa0, 23, r5
cmp r5, #0x60
ble set_sdram_150mhz
I2C_READ 0xa0, 9, r5
cmp r5, #0x60
ble set_sdram_150mhz
orr r3, r3, #(CCR_100MHZ_DIVISOR << 16)
b sdram_divisor_set
set_sdram_150mhz:
orr r3, r3, #(CCR_150MHZ_DIVISOR << 16)
sdram_divisor_set:
ldr r0, =CCR
mov r1, r3
mov r3, #0x0
mcr p15, 0, r0, c7, c10, 4 // DCU drain instruction
b clk_stab
// wait for some time so that clock gets stabilized
// make this code aligned at 32 bytes so that it is aligned on prefatch boundary
.p2align 5
clk_stab:
str r1, [r0] // Store to clock control Register
clk_stab_loop:
add r3, r3, #1
cmp r3, #0x200
bne clk_stab_loop
b clk_stab_done
.p2align 5
clk_stab_done:
// now DRAM IO config registers
ldr r0, =DDR_RDDLYSEL_RECEN
ldr r1, =DDR_RDDLYSEL_RECEN_VAL
str r1, [r0]
ldr r0, =DDR_RX_DLL
ldr r1, =DDR_RX_DLL_VAL
str r1, [r0]
ldr r0, =DDR_RX_DESKEW
ldr r1, =DDR_RX_DESKEW_VAL
str r1, [r0]
/*Rcomp Initialisation
Select Stength for Pin Groups */
ldr r0, =CR0_DSTRENGTHSEL
ldr r1, =0x036db6db @ rcv 1.5x rest 1.5x
str r1, [r0]
/* Program Rcomp offset registers to 0 (until characterised values are available)
Bit[15] = Sign for pulldown
Bit[14:8] = Value for Pulldown
Bit[7] = Sign for pullup
Bit[6:0] = Value for Pullup */
ldr r1, =0x00000000
ldr r0, =CR0_DDQRCOMP @ DQ/DQS offset
str r1, [r0]
ldr r0, =CR0_DCTLRCOMP @ MA/BA/RAS#/CAS#/WE# offset
str r1, [r0]
ldr r0, =CR0_DRCVRCOMP @ RCV offset
str r1, [r0]
ldr r0, =CR0_DCKERCOMP @ CKE offset
str r1, [r0]
ldr r0, =CR0_DCSRCOMP @ CS# offset
str r1, [r0]
ldr r0, =CR0_DCKRCOMP @ CK/CK# offset [31:16 for X16, 15:0 for x8]
str r1, [r0]
/* Select x8 or x16 slew compensation for CKE, CS, CK */
ldr r0, =CR0_DX8X16CKECSCKSEL
ldr r1, =0x11111111 @ for x8 slew compensation
str r1, [r0]
/* Select rcomp Period */
ldr r0, =CR0_RCOMPPRD
ldr r1, =0x00000000 @ for period = 2097152 clock cyles
str r1, [r0]
/* set Dig Filter Clamp */
ldr r0, =CR0_DIGFIL
ldr r1, =0x00000000 @ for no filter
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -