plf_io.h

基于ecos的redboot

        /* Respond to I/O space & Memory transactions.                */ \
        HAL_WRITE_UINT32(SA110_PCI_CFG_COMMAND,                          \
                         CYG_PCI_CFG_COMMAND_INVALIDATE                  \
                         |CYG_PCI_CFG_COMMAND_IO                         \
                         |CYG_PCI_CFG_COMMAND_MEMORY                     \
                         |CYG_PCI_CFG_COMMAND_MASTER);                   \
    }                                                                    \
    /* Signal PCI_init_complete                                       */ \
    HAL_READ_UINT32(SA110_CONTROL, __tmp);                               \
    __tmp |= SA110_CONTROL_INIT_COMPLETE;                                \
    HAL_WRITE_UINT32(SA110_CONTROL, __tmp);                              \
                                                                         \
    CYG_MACRO_END


// Compute address necessary to access PCI config space for the given
// bus and device.
#define HAL_PCI_CONFIG_ADDRESS( __bus, __devfn, __offset )               \
    ({                                                                   \
    cyg_uint32 __addr;                                                   \
    cyg_uint32 __dev = CYG_PCI_DEV_GET_DEV(__devfn);                     \
    if (0 == __bus) {                                                    \
        if (0 == __dev) {                                                \
            /* Access self via CSR base */                               \
            __addr = SA110_CONTROL_STATUS_BASE;                          \
        } else {                                                         \
            /* Page 3-17, table 3-5: bits 15-11 generate PCI address */  \
            __addr = SA110_PCI_CONFIG0_BASE | 0x00c00000 | (__dev << 11);\
        }                                                                \
    } else {                                                             \
        __addr = SA110_PCI_CONFIG1_BASE | (__bus << 16) | (__dev << 11); \
    }                                                                    \
    __addr |= CYG_PCI_DEV_GET_FN(__devfn) << 8;                          \
    __addr |= __offset;                                                  \
    __addr;                                                              \
    })

// Read a value from the PCI configuration space of the appropriate
// size at an address composed from the bus, devfn and offset.
#define HAL_PCI_CFG_READ_UINT8( __bus, __devfn, __offset, __val )  \
    HAL_READ_UINT8(HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset), __val)
    
#define HAL_PCI_CFG_READ_UINT16( __bus, __devfn, __offset, __val ) \
    HAL_READ_UINT16(HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset), __val)

#define HAL_PCI_CFG_READ_UINT32( __bus, __devfn, __offset, __val ) \
    HAL_READ_UINT32(HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset), __val)

// Write a value to the PCI configuration space of the appropriate
// size at an address composed from the bus, devfn and offset.
#define HAL_PCI_CFG_WRITE_UINT8( __bus, __devfn, __offset, __val )  \
    HAL_WRITE_UINT8(HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset), __val)

#define HAL_PCI_CFG_WRITE_UINT16( __bus, __devfn, __offset, __val ) \
    HAL_WRITE_UINT16(HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset), __val)

#define HAL_PCI_CFG_WRITE_UINT32( __bus, __devfn, __offset, __val ) \
    HAL_WRITE_UINT32(HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset), __val)

//-----------------------------------------------------------------------------
// Resources

// Map PCI device resources starting from these addresses in PCI space.
#define HAL_PCI_ALLOC_BASE_MEMORY (EBSA_SDRAM_PCI_SIZE+EBSA_CSR_MEM_PCI_SIZE)
#define HAL_PCI_ALLOC_BASE_IO     (EBSA_CSR_IO_PCI_SIZE)

// This is where the PCI spaces are mapped in the CPU's address space.
#define HAL_PCI_PHYSICAL_MEMORY_BASE    0x80000000
#define HAL_PCI_PHYSICAL_IO_BASE        0x7c000000

// Translate the PCI interrupt requested by the device (INTA#, INTB#,
// INTC# or INTD#) to the associated CPU interrupt (i.e., HAL vector).
#define HAL_PCI_TRANSLATE_INTERRUPT( __bus, __devfn, __vec, __valid)          \
    CYG_MACRO_START                                                           \
    cyg_uint8 __req;                                                          \
    HAL_PCI_CFG_READ_UINT8(__bus, __devfn, CYG_PCI_CFG_INT_PIN, __req);       \
    if (0 != __req) {                                                         \
        /* Interrupt assignment as 21285 sees them. (From                 */  \
        /* EBSA285 Eval Board Reference Manual, 3.4 Interrupt Assignment) */  \
        CYG_ADDRWORD __translation[4] = {                                     \
            CYGNUM_HAL_INTERRUPT_IRQ_IN_1,  /* INTC# */                       \
            CYGNUM_HAL_INTERRUPT_IRQ_IN_0,  /* INTB# */                       \
            CYGNUM_HAL_INTERRUPT_PCI_IRQ,   /* INTA# */                       \
            CYGNUM_HAL_INTERRUPT_IRQ_IN_3}; /* INTD# */                       \
                                                                              \
        /* The PCI lines from the different slots are wired like this  */     \
        /* on the PCI backplane:                                       */     \
        /*                pin6A     pin7B    pin7A   pin8B             */     \
        /* System Slot    INTA#     INTB#    INTC#   INTD#             */     \
        /* I/O Slot 1     INTB#     INTC#    INTD#   INTA#             */     \
        /* I/O Slot 2     INTC#     INTD#    INTA#   INTB#             */     \
        /* I/O Slot 3     INTD#     INTA#    INTB#   INTC#             */     \
        /* I/O Slot 4     INTA#     INTB#    INTC#   INTD#             */     \
        /*                                                             */     \
        /* (From PCI Development Backplane, 3.2.2 Interrupts)          */     \
        /*                                                             */     \
        /* Devsel signals are wired to, resulting in device IDs:       */     \
        /* I/O Slot 1     AD19 / dev 8       [(8+1)&3 = 1]             */     \
        /* I/O Slot 2     AD18 / dev 7       [(7+1)&3 = 0]             */     \
        /* I/O Slot 3     AD17 / dev 6       [(6+1)&3 = 3]             */     \
        /* I/O Slot 4     AD16 / dev 5       [(5+1)&3 = 2]             */     \
        /*                                                             */     \
        /* (From PCI Development Backplane, 3.2.1 General)             */     \
        /*                                                             */     \
        /* The observant reader will notice that the array does not    */     \
        /* match the table of how interrupts are wired. The array      */     \
        /* does however match observed behavior of the hardware:       */     \
        /*                                                             */     \
        /* Observed interrupts with an Intel ethernet card             */     \
        /* put in the slots in turn and set to generate interrupts:    */     \
        /*  slot 1/intA# (dev 8): caused host INTB#                    */     \
        /*  slot 2/intA# (dev 7): caused host INTC#                    */     \
        /*  slot 3/intA# (dev 6): caused host INTD#                    */     \
        /*  slot 4/intA# (dev 5): caused host INTA#                    */     \
                                                                              \
        __vec = __translation[((__req+CYG_PCI_DEV_GET_DEV(__devfn))&3)];      \
        __valid = true;                                                       \
    } else {                                                                  \
        /* Device will not generate interrupt requests. */                    \
        __valid = false;                                                      \
    }                                                                         \
    CYG_MACRO_END

//-----------------------------------------------------------------------------
// end of plf_io.h
#endif // CYGONCE_PLF_IO_H