hal_ebsa285.h

基于ecos的redboot

 */
#define SA110_UART_DISABLED                      0x00000000
#define SA110_UART_ENABLED                       0x00000001
#define SA110_UART_ENABLE_MASK                   0x00000001
#define SA110_SIR_DISABLED                       0x00000000
#define SA110_SIR_ENABLED                        0x00000002
#define SA110_SIR_ENABLE_MASK                    0x00000002
#define SA110_SIR_PULSE_WIDTH_BIT_RATE           0x00000000
#define SA110_SIR_PULSE_WIDTH_MAX_CLK            0x00000004

/*
 * SA-110 UART Flag Register bit masks
 */
#define SA110_TX_IDLE                            0x00000000
#define SA110_TX_BUSY                            0x00000008
#define SA110_TX_BUSY_MASK                       0x00000008
#define SA110_RX_FIFO_FULL                       0x00000000
#define SA110_RX_FIFO_EMPTY                      0x00000010
#define SA110_RX_FIFO_STATUS_MASK                0x00000010
#define SA110_TX_FIFO_READY                      0x00000000
#define SA110_TX_FIFO_BUSY                       0x00000020
#define SA110_TX_FIFO_STATUS_MASK                0x00000020

/*
 * SA-110 IRQ Controller Registers
 */
#define SA110_IRQCONT_IRQSTATUS_o                0x180
#define SA110_IRQCONT_IRQRAWSTATUS_o             0x184
#define SA110_IRQCONT_IRQENABLE_o                0x188
#define SA110_IRQCONT_IRQENABLESET_o             0x188
#define SA110_IRQCONT_IRQENABLECLEAR_o           0x18C
#define SA110_IRQCONT_IRQSOFT_o                  0x190
#define SA110_IRQCONT_FIQSTATUS_o                0x280
#define SA110_IRQCONT_FIQRAWSTATUS_o             0x284
#define SA110_IRQCONT_FIQENABLE_o                0x288
#define SA110_IRQCONT_FIQENABLESET_o             0x288
#define SA110_IRQCONT_FIQENABLECLEAR_o           0x28C
#define SA110_IRQCONT_FIQSOFT_o                  0x290

#define SA110_IRQCONT_IRQSTATUS                  SA110_REGISTER(SA110_IRQCONT_IRQSTATUS_o)
#define SA110_IRQCONT_IRQRAWSTATUS               SA110_REGISTER(SA110_IRQCONT_IRQRAWSTATUS_o)
#define SA110_IRQCONT_IRQENABLE                  SA110_REGISTER(SA110_IRQCONT_IRQENABLE_o)
#define SA110_IRQCONT_IRQENABLESET               SA110_REGISTER(SA110_IRQCONT_IRQENABLESET_o)
#define SA110_IRQCONT_IRQENABLECLEAR             SA110_REGISTER(SA110_IRQCONT_IRQENABLECLEAR_o)
#define SA110_IRQCONT_IRQSOFT                    SA110_REGISTER(SA110_IRQCONT_IRQSOFT_o)
#define SA110_IRQCONT_FIQSTATUS                  SA110_REGISTER(SA110_IRQCONT_FIQSTATUS_o)
#define SA110_IRQCONT_FIQRAWSTATUS               SA110_REGISTER(SA110_IRQCONT_FIQRAWSTATUS_o)
#define SA110_IRQCONT_FIQENABLE                  SA110_REGISTER(SA110_IRQCONT_FIQENABLE_o)
#define SA110_IRQCONT_FIQENABLESET               SA110_REGISTER(SA110_IRQCONT_FIQENABLESET_o)
#define SA110_IRQCONT_FIQENABLECLEAR             SA110_REGISTER(SA110_IRQCONT_FIQENABLECLEAR_o)
#define SA110_IRQCONT_FIQSOFT                    SA110_REGISTER(SA110_IRQCONT_FIQSOFT_o)

/*
 * SA-110 Timer Control Registers
 */
#define SA110_TIMER_BASE_o 			 0x300
#define SA110_TIMER1_BASE_o 			 (SA110_TIMER_BASE_o + 0x00)
#define SA110_TIMER2_BASE_o 			 (SA110_TIMER_BASE_o + 0x20)
#define SA110_TIMER3_BASE_o 			 (SA110_TIMER_BASE_o + 0x40)
#define SA110_TIMER4_BASE_o 			 (SA110_TIMER_BASE_o + 0x60)

#define SA110_TIMER1_LOAD_o			 (SA110_TIMER1_BASE_o + 0x0)
#define SA110_TIMER1_VALUE_o  			 (SA110_TIMER1_BASE_o + 0x4)
#define SA110_TIMER1_CONTROL_o			 (SA110_TIMER1_BASE_o + 0x8)
#define SA110_TIMER1_CLEAR_o  			 (SA110_TIMER1_BASE_o + 0xc)
#define SA110_TIMER2_LOAD_o			 (SA110_TIMER2_BASE_o + 0x0)
#define SA110_TIMER2_VALUE_o  			 (SA110_TIMER2_BASE_o + 0x4)
#define SA110_TIMER2_CONTROL_o			 (SA110_TIMER2_BASE_o + 0x8)
#define SA110_TIMER2_CLEAR_o  			 (SA110_TIMER2_BASE_o + 0xc)
#define SA110_TIMER3_LOAD_o			 (SA110_TIMER3_BASE_o + 0x0)
#define SA110_TIMER3_VALUE_o  			 (SA110_TIMER3_BASE_o + 0x4)
#define SA110_TIMER3_CONTROL_o			 (SA110_TIMER3_BASE_o + 0x8)
#define SA110_TIMER3_CLEAR_o  			 (SA110_TIMER3_BASE_o + 0xc)
#define SA110_TIMER4_LOAD_o			 (SA110_TIMER4_BASE_o + 0x0)
#define SA110_TIMER4_VALUE_o  			 (SA110_TIMER4_BASE_o + 0x4)
#define SA110_TIMER4_CONTROL_o			 (SA110_TIMER4_BASE_o + 0x8)
#define SA110_TIMER4_CLEAR_o  			 (SA110_TIMER4_BASE_o + 0xc)

#define SA110_TIMER1_LOAD			 SA110_REGISTER(SA110_TIMER1_LOAD_o)
#define SA110_TIMER1_VALUE			 SA110_REGISTER(SA110_TIMER1_VALUE_o)
#define SA110_TIMER1_CONTROL			 SA110_REGISTER(SA110_TIMER1_CONTROL_o)
#define SA110_TIMER1_CLEAR			 SA110_REGISTER(SA110_TIMER1_CLEAR_o)
#define SA110_TIMER2_LOAD			 SA110_REGISTER(SA110_TIMER2_LOAD_o)
#define SA110_TIMER2_VALUE			 SA110_REGISTER(SA110_TIMER2_VALUE_o)
#define SA110_TIMER2_CONTROL			 SA110_REGISTER(SA110_TIMER2_CONTROL_o)
#define SA110_TIMER2_CLEAR			 SA110_REGISTER(SA110_TIMER2_CLEAR_o)
#define SA110_TIMER3_LOAD			 SA110_REGISTER(SA110_TIMER3_LOAD_o)
#define SA110_TIMER3_VALUE			 SA110_REGISTER(SA110_TIMER3_VALUE_o)
#define SA110_TIMER3_CONTROL			 SA110_REGISTER(SA110_TIMER3_CONTROL_o)
#define SA110_TIMER3_CLEAR			 SA110_REGISTER(SA110_TIMER3_CLEAR_o)
#define SA110_TIMER4_LOAD			 SA110_REGISTER(SA110_TIMER4_LOAD_o)
#define SA110_TIMER4_VALUE			 SA110_REGISTER(SA110_TIMER4_VALUE_o)
#define SA110_TIMER4_CONTROL			 SA110_REGISTER(SA110_TIMER4_CONTROL_o)
#define SA110_TIMER4_CLEAR			 SA110_REGISTER(SA110_TIMER4_CLEAR_o)

/* Timer bits */
#define SA110_TIMER_CONTROL_SCALE_1              0x00000000
#define SA110_TIMER_CONTROL_SCALE_16             0x00000004
#define SA110_TIMER_CONTROL_SCALE_256            0x00000008
#define SA110_TIMER_CONTROL_SCALE_EXT            0x0000000c
#define SA110_TIMER_CONTROL_MODE                 0x00000040
#define SA110_TIMER_CONTROL_ENABLE               0x00000080

/*
 * IRQ Controller IRQ Numbers
 */
#define SA110_IRQ_MIN                            0

#define SA110_IRQ_RSV0                           0
#define SA110_IRQ_SOFT_INTERRUPT                 1
#define SA110_IRQ_CONSOLE_RX                     2
#define SA110_IRQ_CONSOLE_TX                     3
#define SA110_IRQ_TIMER_1                        4
#define SA110_IRQ_TIMER_2                        5
#define SA110_IRQ_TIMER_3                        6
#define SA110_IRQ_TIMER_4                        7
#define SA110_IRQ_IRQ_IN_I_0                     8
#define SA110_IRQ_IRQ_IN_I_1                     9
#define SA110_IRQ_IRQ_IN_I_2                     10
#define SA110_IRQ_IRQ_IN_I_3                     11
#define SA110_IRQ_XCS_I_0                        12
#define SA110_IRQ_XCS_I_1                        13
#define SA110_IRQ_XCS_I_2                        14
#define SA110_IRQ_DOORBELL_FROM_HOST             15
#define SA110_IRQ_DMA_CHAN_1                     16
#define SA110_IRQ_DMA_CHAN_2                     17
#define SA110_IRQ_PIC_IRQ_I                      18
#define SA110_IRQ_PMCSR_WRITE_BY_HOST            19
#define SA110_IRQ_RSV1                           20
#define SA110_IRQ_RSV2                           21
#define SA110_IRQ_START_BIST                     22
#define SA110_IRQ_RECEIVED_SERR                  23
#define SA110_IRQ_SDRAM_PARITY                   24
#define SA110_IRQ_I20_INBOUND_POST_LIST          25
#define SA110_IRQ_RSV3                           26
#define SA110_IRQ_DISCARD_TIMER_EXPIRED          27
#define SA110_IRQ_DATA_PARITY_ERROR              28
#define SA110_IRQ_MASTER_ABORT                   29
#define SA110_IRQ_TARGET_ABORT                   30
#define SA110_IRQ_PARITY_ERROR                   31

#define SA110_IRQ_MAX                            31
#define NUM_SA110_INTERRUPTS                     SA110_IRQ_MAX - SA110_IRQ_MIN + 1
#define SA110_IRQ_INTSRC_MASK(irq_nr)            (1 << (irq_nr))


/*
 * SA110 IRQSOFT/FIQSOFT Register bit fields
 */
#define SA110_IRQSOFT_RAW_BIT_MASK               0x00000001

/*
 * SA-110 Miscellaneous Registers.
 */
#define SA110_XBUS_CYCLE_ARBITER_o               0x148
#define SA110_XBUS_IO_STROBE_MASK_o              0x14c

#define SA110_XBUS_CYCLE_ARBITER                 SA110_REGISTER(SA110_XBUS_CYCLE_ARBITER_o)
#define SA110_XBUS_IO_STROBE_MASK                SA110_REGISTER(SA110_XBUS_IO_STROBE_MASK_o)

#define SA110_XBUS_CYCLE_ARBITER_ENABLED         0x00800000

#define SA110_XBUS_XCS2                          0x40012000
#define SA110_XBUS_XCS2_PCI_DISABLE              0x40

// -------------------------------------------------------------------------
// MMU initialization:
// 
// These structures are laid down in memory to define the translation
// table.  For usage, see the memory setup in ebsa285_misc.c in this
// component.  hal_bsp_mmu_init()
// 

/*
 * SA-1100 Translation Table Base Bit Masks */
#define ARM_TRANSLATION_TABLE_MASK               0xFFFFC000

/*
 * SA-1100 Domain Access Control Bit Masks
 */
#define ARM_ACCESS_TYPE_NO_ACCESS(domain_num)    (0x0 << (domain_num)*2)
#define ARM_ACCESS_TYPE_CLIENT(domain_num)       (0x1 << (domain_num)*2)
#define ARM_ACCESS_TYPE_MANAGER(domain_num)      (0x3 << (domain_num)*2)

// These are only useful in C, so:
#ifndef  __ASSEMBLER__

struct ARM_MMU_FIRST_LEVEL_FAULT {
    int id : 2;
    int sbz : 30;
};
#define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0

struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE {
    int id : 2;
    int imp : 2;
    int domain : 4;
    int sbz : 1;
    int base_address : 23;
};
#define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1

struct ARM_MMU_FIRST_LEVEL_SECTION {
    int id : 2;
    int b : 1;
    int c : 1;
    int imp : 1;
    int domain : 4;
    int sbz0 : 1;
    int ap : 2;
    int sbz1 : 8;
    int base_address : 12;
};
#define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2

struct ARM_MMU_FIRST_LEVEL_RESERVED {
    int id : 2;
    int sbz : 30;
};
#define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3

#define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \
   (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2))

#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base,              \
                        cacheable, bufferable, perm)                      \
    CYG_MACRO_START                                                       \
        register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc;               \
                                                                          \
        desc.word = 0;                                                    \
        desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID;                 \
        desc.section.domain = 0;                                          \
        desc.section.c = (cacheable);                                     \
        desc.section.b = (bufferable);                                    \
        desc.section.ap = (perm);                                         \
        desc.section.base_address = (actual_base);                        \
        *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
                            = desc.word;                                  \
    CYG_MACRO_END

union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
    unsigned long word;
    struct ARM_MMU_FIRST_LEVEL_FAULT fault;
    struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
    struct ARM_MMU_FIRST_LEVEL_SECTION section;
    struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
};

#endif /* __ASSEMBLER__ */

#define ARM_UNCACHEABLE                         0
#define ARM_CACHEABLE                           1
#define ARM_UNBUFFERABLE                        0
#define ARM_BUFFERABLE                          1

#define ARM_ACCESS_PERM_NONE_NONE               0
#define ARM_ACCESS_PERM_RO_NONE                 0
#define ARM_ACCESS_PERM_RO_RO                   0
#define ARM_ACCESS_PERM_RW_NONE                 1
#define ARM_ACCESS_PERM_RW_RO                   2
#define ARM_ACCESS_PERM_RW_RW                   3


/*---------------------------------------------------------------------------*/
/* end of hal_ebsa285.h                                                         */
#endif /* CYGONCE_HAL_EBSA285_H */