hal_ebsa285.h

基于ecos的redboot

#ifndef CYGONCE_HAL_EBSA285_H
#define CYGONCE_HAL_EBSA285_H

/*=============================================================================
//
//      hal_ebsa285.h
//
//      HAL Description of SA-110 and 21285 control registers
//      and ARM memory control in general.
//
//=============================================================================
//####COPYRIGHTBEGIN####
//                                                                          
// -------------------------------------------                              
// The contents of this file are subject to the Red Hat eCos Public License 
// Version 1.1 (the "License"); you may not use this file except in         
// compliance with the License.  You may obtain a copy of the License at    
// http://www.redhat.com/                                                   
//                                                                          
// Software distributed under the License is distributed on an "AS IS"      
// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
// License for the specific language governing rights and limitations under 
// the License.                                                             
//                                                                          
// The Original Code is eCos - Embedded Configurable Operating System,      
// released September 30, 1998.                                             
//                                                                          
// The Initial Developer of the Original Code is Red Hat.                   
// Portions created by Red Hat are                                          
// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.                             
// All Rights Reserved.                                                     
// -------------------------------------------                              
//                                                                          
//####COPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    hmt
// Contributors: hmt
// Date:         1999-04-19
// Purpose:      Intel EBSA285 hardware description
// Description:
// Usage:        #include <cyg/hal/hal_ebsa285.h>
//
//####DESCRIPTIONEND####
//
//===========================================================================*/

// Note: these defintions match the documentation, thus no attempt is made
// to santise (mangle) the names against namespace pollution.  Also, care should be
// taken to keep this clean for use in assembly code (no "C" constructs).


#define SZ_1K           0x00000400
#define SZ_2K           0x00000800
#define SZ_4K           0x00001000
#define SZ_8K           0x00002000
#define SZ_16K          0x00004000
#define SZ_32K          0x00008000
#define SZ_64K          0x00010000
#define SZ_128K         0x00020000
#define SZ_256K         0x00040000
#define SZ_512K         0x00080000
#define SZ_1M           0x00100000
#define SZ_2M           0x00200000
#define SZ_4M           0x00400000
#define SZ_8M           0x00800000
#define SZ_16M          0x01000000
#define SZ_32M          0x02000000
#define SZ_64M          0x04000000
#define SZ_128M         0x08000000
#define SZ_256M         0x10000000
#define SZ_512M         0x20000000
#define SZ_1G           0x40000000

#ifdef __ASSEMBLER__

#define REG8_VAL(a)  (a)
#define REG16_VAL(a) (a)
#define REG32_VAL(a) (a)

#define REG8_PTR(a)  (a)
#define REG16_PTR(a) (a)
#define REG32_PTR(a) (a)

#else /* __ASSEMBLER__ */

#define REG8_VAL(a)  ((unsigned char)(a))
#define REG16_VAL(a) ((unsigned short)(a))
#define REG32_VAL(a) ((unsigned int)(a))

#define REG8_PTR(a)  ((volatile unsigned char *)(a))
#define REG16_PTR(a) ((volatile unsigned long *)(a))
#define REG32_PTR(a) ((volatile unsigned long *)(a))

#endif /* __ASSEMBLER__ */

//
// Memory Layout
//
#define EBSA285_RAM_BANK0_BASE 0x00000000

/*
 * SA-110 Cache and MMU Control Registers
 *
 * Accessed through coprocessor instructions.
 */
#define SA110_ID_REGISTER                        0
#define SA110_CONTROL_REGISTER                   1
#define SA110_TRANSLATION_TABLE_BASE_REGISTER    2
#define SA110_DOMAIN_ACCESS_CONTROL_REGISTER     3
#define SA110_FAULT_STATUS_REGISTER              5
#define SA110_FAULT_ADDRESS_REGISTER             6
#define SA110_CACHE_OPERATIONS_REGISTER          7
#define SA110_TLB_OPERATIONS_REGISTER            8
#define SA110_TEST_CLOCK_AND_IDLE_REGISTER       15

/*
 * SA-110 Cache and MMU Definitions
 */
#define SA110_ICACHE_SIZE                       SZ_16K
#define SA110_DCACHE_SIZE                       SZ_16K
#define SA110_ICACHE_LINESIZE_BYTES             32
#define SA110_DCACHE_LINESIZE_BYTES             32
#define SA110_ICACHE_LINESIZE_WORDS             8
#define SA110_DCACHE_LINESIZE_WORDS             8
#define SA110_ICACHE_WAYS                       32
#define SA110_DCACHE_WAYS                       32
#define SA110_ICACHE_LINE_BASE(p)               REG32_PTR((unsigned long)(p) & \
                                                           ~(SA110_ICACHE_LINESIZE_BYTES - 1))
#define SA110_DCACHE_LINE_BASE(p)               REG32_PTR((unsigned long)(p) & \
                                                           ~(SA110_DCACHE_LINESIZE_BYTES - 1))

#define SA110_ZEROS_BANK_BASE                  (0x50000000)

#define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 	SZ_16K



/*
 * SA-110 Cache and MMU ID Register value
 */
#define SA110_ID_MASK                            0xFFFFFFF0
#define SA110_ID_VALUE                           0x4401a100

/*
 * SA-110 Cache Control Register Bit Fields and Masks
 */
#define SA110_MMU_DISABLED                       0x00000000
#define SA110_MMU_ENABLED                        0x00000001
#define SA110_MMU_MASK                           0x00000001
#define SA110_ADDRESS_FAULT_DISABLED             0x00000000
#define SA110_ADDRESS_FAULT_ENABLED              0x00000002
#define SA110_ADDRESS_FAULT_MASK                 0x00000002
#define SA110_DATA_CACHE_DISABLED                0x00000000
#define SA110_DATA_CACHE_ENABLED                 0x00000004
#define SA110_DATA_CACHE_MASK                    0x00000004
#define SA110_WRITE_BUFFER_DISABLED              0x00000000
#define SA110_WRITE_BUFFER_ENABLED               0x00000008
#define SA110_WRITE_BUFFER_MASK                  0x00000008
#define SA110_LITTLE_ENDIAN                      0x00000000
#define SA110_BIG_ENDIAN                         0x00000080
#define SA110_ACCESS_CHECKS_SYSTEM               0x00000100
#define SA110_ACCESS_CHECKS_ROM                  0x00000200
#define SA110_INSTRUCTION_CACHE_DISABLED         0x00000000
#define SA110_INSTRUCTION_CACHE_ENABLED          0x00001000
#define SA110_INSTRUCTION_CACHE_MASK             0x00001000

/*
 * SA-110 Translation Table Base Bit Masks
 */
#define SA110_TRANSLATION_TABLE_MASK             0xFFFFC000

/*
 * SA-110 Domain Access Control Bit Masks
 */
#define SA110_DOMAIN_0_MASK                      0x00000003
#define SA110_DOMAIN_1_MASK                      0x0000000C
#define SA110_DOMAIN_2_MASK                      0x00000030
#define SA110_DOMAIN_3_MASK                      0x000000C0
#define SA110_DOMAIN_4_MASK                      0x00000300
#define SA110_DOMAIN_5_MASK                      0x00000C00
#define SA110_DOMAIN_6_MASK                      0x00003000
#define SA110_DOMAIN_7_MASK                      0x0000C000
#define SA110_DOMAIN_8_MASK                      0x00030000
#define SA110_DOMAIN_9_MASK                      0x000C0000
#define SA110_DOMAIN_10_MASK                     0x00300000
#define SA110_DOMAIN_11_MASK                     0x00C00000
#define SA110_DOMAIN_12_MASK                     0x03000000
#define SA110_DOMAIN_13_MASK                     0x0C000000
#define SA110_DOMAIN_14_MASK                     0x30000000
#define SA110_DOMAIN_15_MASK                     0xC0000000

/*
 * SA-110 Fault Status Bit Masks
 */
#define SA110_FAULT_STATUS_MASK                  0x0000000F
#define SA110_DOMAIN_MASK                        0x000000F0

/*
 * SA-110 Cache Control Operations Definitions
 */
#define SA110_FLUSH_CACHE_INST_DATA_OPCODE       0x0
#define SA110_FLUSH_CACHE_INST_DATA_RM           0x7
#define SA110_FLUSH_CACHE_INST_OPCODE            0x0
#define SA110_FLUSH_CACHE_INST_RM                0x5
#define SA110_FLUSH_CACHE_DATA_OPCODE            0x0
#define SA110_FLUSH_CACHE_DATA_RM                0x6
#define SA110_FLUSH_CACHE_DATA_SINGLE_OPCODE     0x1
#define SA110_FLUSH_CACHE_DATA_SINGLE_RM         0x6
#define SA110_CLEAN_CACHE_DATA_ENTRY_OPCODE      0x1
#define SA110_CLEAN_CACHE_DATA_ENTRY_RM          0xA
#define SA110_DRAIN_CACHE_WRITE_BUFFER_OPCODE    0x4
#define SA110_DRAIN_CACHE_WRITE_BUFFER_RM        0xA

/*
 * SA-110 TLB Operations Definitions
 */
#define SA110_FLUSH_INST_DATA_TLB_OPCODE         0x0
#define SA110_FLUSH_INST_DATA_TLB_RM             0x7
#define SA110_FLUSH_INST_TLB_OPCODE              0x0
#define SA110_FLUSH_INST_TLB_RM                  0x5
#define SA110_FLUSH_DATA_TLB_OPCODE              0x0
#define SA110_FLUSH_DATA_TLB_RM                  0x6
#define SA110_FLUSH_DATA_ENTRY_TLB_OPCODE        0x1
#define SA110_FLUSH_DATA_ENTRY_TLB_RM            0x6

/*
 * SA-110 Test, Clock and Idle Control Definition
 */
#define SA110_ICACHE_ODD_WORD_LOADING_OPCODE     0x1
#define SA110_ICACHE_ODD_WORD_LOADING_RM         0x1
#define SA110_ICACHE_EVEN_WORD_LOADING_OPCODE    0x1
#define SA110_ICACHE_EVEN_WORD_LOADING_RM        0x2
#define SA110_ICACHE_CLEAR_LFSR_OPCODE           0x1
#define SA110_ICACHE_CLEAR_LFSR_RM               0x4
#define SA110_ENABLE_CLOCK_SWITCHING_OPCODE      0x2
#define SA110_ENABLE_CLOCK_SWITCHING_RM          0x1
#define SA110_DISABLE_CLOCK_SWITCHING_OPCODE     0x2
#define SA110_DISABLE_CLOCK_SWITCHING_RM         0x2
#define SA110_DISABLE_mCLK_OUTPUT_OPCODE         0x2
#define SA110_DISABLE_mCLK_OUTPUT_RM             0x4
#define SA110_WAIT_FOR_INTERRUPT_OPCODE          0x2
#define SA110_WAIT_FOR_INTERRUPT_RM              0x8


/*
 * SA-110 Control and Status Register Base Definitions
 */
#define SA110_CONTROL_STATUS_BASE                0x42000000
#define SA110_REGISTER(x)                        REG32_PTR(SA110_CONTROL_STATUS_BASE + (x))

#define SA110_PCI_CONFIG0_BASE                   0x7b000000
#define SA110_PCI_CONFIG1_BASE                   0x7a000000

/*
 * These are standard PCI configuration offsets with base at 
 * SA110_CONTROL_STATUS_BASE - a memory-mapped version of the board's
 * own PCI configuration registers. 
 * (see io_pci_cfg.h for other registers)
 */

#define SA110_PCI_CFG_COMMAND_o                 0x04
#define SA110_PCI_CFG_INT_LINE_o                0x3c
#define SA110_PCI_CFG_CSR_MEM_BAR_o             0x10 // BAR[0]
#define SA110_PCI_CFG_CSR_IO_BAR_o              0x14 // BAR[1]
#define SA110_PCI_CFG_SDRAM_BAR_o               0x18 // BAR[2]