📄 hal_intr.h
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#ifndef CYGONCE_HAL_INTR_H
#define CYGONCE_HAL_INTR_H
//==========================================================================
//
// hal_intr.h
//
// HAL Interrupt and clock support
//
//==========================================================================
//####COPYRIGHTBEGIN####
//
// -------------------------------------------
// The contents of this file are subject to the Red Hat eCos Public License
// Version 1.1 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://www.redhat.com/
//
// Software distributed under the License is distributed on an "AS IS"
// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
// License for the specific language governing rights and limitations under
// the License.
//
// The Original Code is eCos - Embedded Configurable Operating System,
// released September 30, 1998.
//
// The Initial Developer of the Original Code is Red Hat.
// Portions created by Red Hat are
// Copyright (C) 1998, 1999, 2000, 2001 Red Hat, Inc.
// All Rights Reserved.
// -------------------------------------------
//
//####COPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg, gthomas
// Contributors: nickg, gthomas,
// jlarmour
// Date: 1999-02-20
// Purpose: Define Interrupt support
// Description: The macros defined here provide the HAL APIs for handling
// interrupts and the clock.
//
// Usage: #include <cyg/hal/hal_intr.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//==========================================================================
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
// This is to allow a variant to decide that there is no platform-specific
// interrupts file; and that in turn can be overridden by a platform that
// refines the variant's ideas.
#ifdef CYGBLD_HAL_PLF_INTS_H
# include CYGBLD_HAL_PLF_INTS_H // should include variant data as required
#else
# ifdef CYGBLD_HAL_VAR_INTS_H
# include CYGBLD_HAL_VAR_INTS_H
# else
# include <cyg/hal/hal_platform_ints.h> // default less-complex platforms
# endif
#endif
// Spurious interrupt (no interrupt source could be found)
#define CYGNUM_HAL_INTERRUPT_NONE -1
//--------------------------------------------------------------------------
// ARM exception vectors.
// These vectors correspond to VSRs. These values are the ones to use for
// HAL_VSR_GET/SET
#define CYGNUM_HAL_VECTOR_RESET 0
#define CYGNUM_HAL_VECTOR_UNDEF_INSTRUCTION 1
#define CYGNUM_HAL_VECTOR_SOFTWARE_INTERRUPT 2
#define CYGNUM_HAL_VECTOR_ABORT_PREFETCH 3
#define CYGNUM_HAL_VECTOR_ABORT_DATA 4
#define CYGNUM_HAL_VECTOR_reserved 5
#define CYGNUM_HAL_VECTOR_IRQ 6
#define CYGNUM_HAL_VECTOR_FIQ 7
#define CYGNUM_HAL_VSR_MIN 0
#define CYGNUM_HAL_VSR_MAX 7
#define CYGNUM_HAL_VSR_COUNT 8
// Exception vectors. These are the values used when passed out to an
// external exception handler using cyg_hal_deliver_exception()
#define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION \
CYGNUM_HAL_VECTOR_UNDEF_INSTRUCTION
#define CYGNUM_HAL_EXCEPTION_INTERRUPT \
CYGNUM_HAL_VECTOR_SOFTWARE_INTERRUPT
#define CYGNUM_HAL_EXCEPTION_CODE_ACCESS CYGNUM_HAL_VECTOR_ABORT_PREFETCH
#define CYGNUM_HAL_EXCEPTION_DATA_ACCESS CYGNUM_HAL_VECTOR_ABORT_DATA
#define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION
#define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_EXCEPTION_DATA_ACCESS
#define CYGNUM_HAL_EXCEPTION_COUNT (CYGNUM_HAL_EXCEPTION_MAX - \
CYGNUM_HAL_EXCEPTION_MIN + 1)
//--------------------------------------------------------------------------
// Static data used by HAL
// ISR tables
externC CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
externC CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
externC CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];
// VSR table
externC CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_COUNT];
// Platform setup memory size (0 if unknown by hardware)
externC CYG_ADDRWORD hal_dram_size;
// what, if anything, this means, is platform dependent:
externC CYG_ADDRWORD hal_dram_type;
#if CYGINT_HAL_ARM_MEM_REAL_REGION_TOP
externC cyg_uint8 *hal_arm_mem_real_region_top( cyg_uint8 *_regionend_ );
# define HAL_MEM_REAL_REGION_TOP( _regionend_ ) \
hal_arm_mem_real_region_top( _regionend_ )
#endif
//--------------------------------------------------------------------------
// Default ISR
// The #define is used to test whether this routine exists, and to allow
// code outside the HAL to call it.
externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
#define HAL_DEFAULT_ISR hal_default_isr
//--------------------------------------------------------------------------
// Interrupt state storage
typedef cyg_uint32 CYG_INTERRUPT_STATE;
//--------------------------------------------------------------------------
// Interrupt control macros
#ifndef __thumb__
// Note: This disables both FIQ and IRQ interrupts!
#define HAL_DISABLE_INTERRUPTS(_old_) \
asm volatile ( \
"mrs %0,cpsr;" \
"mrs r4,cpsr;" \
"orr r4,r4,#0xC0;" \
"msr cpsr,r4" \
: "=r"(_old_) \
: \
: "r4" \
);
#define HAL_ENABLE_INTERRUPTS() \
asm volatile ( \
"mrs r3,cpsr;" \
"bic r3,r3,#0xC0;" \
"msr cpsr,r3" \
: \
: \
: "r3" \
);
#define HAL_RESTORE_INTERRUPTS(_old_) \
asm volatile ( \
"mrs r3,cpsr;" \
"and r4,%0,#0xC0;" \
"bic r3,r3,#0xC0;" \
"orr r3,r3,r4;" \
"msr cpsr,r3" \
: \
: "r"(_old_) \
: "r3", "r4" \
);
#define HAL_QUERY_INTERRUPTS(_old_) \
asm volatile ( \
"mrs r4,cpsr;" \
"and r4,r4,#0xC0;" \
"eor %0,r4,#0xC0;" \
: "=r"(_old_) \
: \
: "r4" \
);
#else // __thumb__
// Thumb mode does not have access to the PSR registers;
#if 0 // These don't seem to always work
#define HAL_DISABLE_INTERRUPTS(_old_) \
asm volatile ( \
"ldr r4,=10f;" \
"bx r4;" \
".code 32;" \
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