pci.h

基于ecos的redboot

#ifndef CYGONCE_PCI_H
#define CYGONCE_PCI_H
//=============================================================================
//
//      pci.h
//
//      PCI library
//
//=============================================================================
//####COPYRIGHTBEGIN####
//                                                                          
// -------------------------------------------                              
// The contents of this file are subject to the Red Hat eCos Public License 
// Version 1.1 (the "License"); you may not use this file except in         
// compliance with the License.  You may obtain a copy of the License at    
// http://www.redhat.com/                                                   
//                                                                          
// Software distributed under the License is distributed on an "AS IS"      
// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
// License for the specific language governing rights and limitations under 
// the License.                                                             
//                                                                          
// The Original Code is eCos - Embedded Configurable Operating System,      
// released September 30, 1998.                                             
//                                                                          
// The Initial Developer of the Original Code is Red Hat.                   
// Portions created by Red Hat are                                          
// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.                             
// All Rights Reserved.                                                     
// -------------------------------------------                              
//                                                                          
//####COPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    jskov, from design by nickg 
// Contributors: jskov
// Date:         1999-08-09
// Purpose:      PCI configuration access
// Usage:
//              #include <cyg/io/pci.h>
// Description: 
//             This library provides a set of routines for accessing 
//             the PCI bus configuration space in a portable manner. 
//             This is provided by two APIs. The high level API (defined
//             by this file) is used by device drivers, or other code, to
//             access the PCI configuration space portably. The low level
//             API (see pci_hw.h) is used  by the PCI library itself
//             to access the hardware in a platform-specific manner and
//             may also be used by device drivers to access the PCI
//             configuration space directly.
//
//####DESCRIPTIONEND####
//
//=============================================================================

#include <cyg/infra/cyg_type.h>
#include <cyg/io/pci_cfg.h>
#include <cyg/io/pci_hw.h>

//------------------------------------------------------------------
// The PCI memory space can span 64 bits, IO space only 32 bits
#ifdef __ARMEB__
typedef CYG_WORD32 CYG_PCI_ADDRESS64;
#else
typedef CYG_WORD64 CYG_PCI_ADDRESS64;
#endif
typedef CYG_WORD32 CYG_PCI_ADDRESS32;

//------------------------------------------------------------------
// Macros for manufacturing and decomposing device ids
typedef CYG_WORD32 cyg_pci_device_id;           // PCI device ID

#define CYG_PCI_DEV_MAKE_ID(__bus,__devfn) (((__bus)<<16)|((__devfn)<<8))
#define CYG_PCI_DEV_GET_BUS(__devid) ((__devid>>16)&0xFF)
#define CYG_PCI_DEV_GET_DEVFN(__devid) ((__devid>>8)&0xFF)

#define CYG_PCI_NULL_DEVID 0xffffffff
#define CYG_PCI_NULL_DEVFN 0xffff

//------------------------------------------------------------------
// PCI device data definitions and structures

typedef enum { 
    CYG_PCI_HEADER_NORMAL = 0, 
    CYG_PCI_HEADER_BRIDGE = 1,
    CYG_PCI_HEADER_CARDBUS_BRIDGE = 2
} cyg_pci_header_type;

typedef struct                          // PCI device data
{
    cyg_pci_device_id devid;            // ID of this device

    // The following fields are read out of the
    // config space for this device.

    cyg_uint16  vendor;                 // vendor ID
    cyg_uint16  device;                 // device ID
    cyg_uint16  command;                // command register
    cyg_uint16  status;                 // status register
    cyg_uint32  class_rev;              // class+revision
    cyg_uint8   cache_line_size;        // cache line size
    cyg_uint8   latency_timer;          // latency timer
    cyg_pci_header_type header_type;    // header type
    cyg_uint8   bist;                   // Built-in Self-Test
    cyg_uint32  base_address[6];        // Memory base address registers

    // The following fields are used by the resource allocation
    // routines to keep track of allocated resources.
    cyg_uint32 num_bars;
        
    cyg_uint32 base_size[6];            // Memory size for each base address
    cyg_uint32 base_map[6];             // Physical address mapped

    CYG_ADDRWORD hal_vector;            // HAL interrupt vector used by
                                        // device if int_line!=0

    // One of the following unions will be filled in according to
    // the value of the header_type field.

    union
    {
        struct
        {
            cyg_uint32  cardbus_cis;    // CardBus CIS Pointer
            cyg_uint16  sub_vendor;     // subsystem vendor id
            cyg_uint16  sub_id;         // subsystem id
            cyg_uint32  rom_address;    // ROM address register
            cyg_uint8   cap_list;       // capability list
            cyg_uint8   reserved1[7];
            cyg_uint8   int_line;       // interrupt line
            cyg_uint8   int_pin;        // interrupt pin
            cyg_uint8   min_gnt;        // timeslice request
            cyg_uint8   max_lat;        // priority-level request
        } normal;
        struct
        {
	    cyg_uint8	pri_bus;		// primary bus number
	    cyg_uint8	sec_bus;		// secondary bus number
	    cyg_uint8	sub_bus;		// subordinate bus number
	    cyg_uint8	sec_latency_timer;	// secondary bus latency
	    cyg_uint8	io_base;
	    cyg_uint8	io_limit;
	    cyg_uint16	sec_status;		// secondary bus status
	    cyg_uint16	mem_base;
	    cyg_uint16	mem_limit;
	    cyg_uint16	prefetch_base;
	    cyg_uint16	prefetch_limit;
	    cyg_uint32	prefetch_base_upper32;
	    cyg_uint32	prefetch_limit_upper32;	
	    cyg_uint16	io_base_upper16;
	    cyg_uint16	io_limit_upper16;
            cyg_uint8   reserved1[4];
            cyg_uint32  rom_address;    	// ROM address register
            cyg_uint8   int_line;       	// interrupt line
            cyg_uint8   int_pin;        	// interrupt pin
	    cyg_uint16	control;		// bridge control
        } bridge;
        struct
        {
            // Not yet supported
        } cardbus_bridge;
    } header;
} cyg_pci_device;
    
//------------------------------------------------------------------------
// Init
externC void cyg_pci_init( void );

//------------------------------------------------------------------------
// Common device configuration access functions