at91rm9200.h

Vxworks下BSP源码

#define AT91C_US0_NER   	0xFFFC0044 // US0 Nb Errors Register
#define AT91C_US0_RTOR  	0xFFFC0024 // US0 Receiver Time-out Register
#define AT91C_US0_XXR   	0xFFFC0048 // US0 XON_XOFF Register
#define AT91C_US0_FIDI  	0xFFFC0040 // US0 FI_DI_Ratio Register
#define AT91C_US0_CR    	0xFFFC0000 // US0 Control Register
#define AT91C_US0_IER   	0xFFFC0008 // US0 Interrupt Enable Register
#define AT91C_US0_IF    	0xFFFC004C // US0 IRDA_FILTER Register
#define AT91C_US0_MR    	0xFFFC0004 // US0 Mode Register
#define AT91C_US0_IDR   	0xFFFC000C // US0 Interrupt Disable Register
#define AT91C_US0_CSR   	0xFFFC0014 // US0 Channel Status Register
#define AT91C_US0_THR   	0xFFFC001C // US0 Transmitter Holding Register
// ========== Register definition for TWI peripheral ========== 
#define AT91C_TWI_RHR   	0xFFFB8030 // TWI Receive Holding Register
#define AT91C_TWI_IDR   	0xFFFB8028 // TWI Interrupt Disable Register
#define AT91C_TWI_SR    	0xFFFB8020 // TWI Status Register
#define AT91C_TWI_CWGR  	0xFFFB8010 // TWI Clock Waveform Generator Register
#define AT91C_TWI_SMR   	0xFFFB8008 // TWI Slave Mode Register
#define AT91C_TWI_CR    	0xFFFB8000 // TWI Control Register
#define AT91C_TWI_THR   	0xFFFB8034 // TWI Transmit Holding Register
#define AT91C_TWI_IMR   	0xFFFB802C // TWI Interrupt Mask Register
#define AT91C_TWI_IER   	0xFFFB8024 // TWI Interrupt Enable Register
#define AT91C_TWI_IADR  	0xFFFB800C // TWI Internal Address Register
#define AT91C_TWI_MMR   	0xFFFB8004 // TWI Master Mode Register
// ========== Register definition for PDC_MCI peripheral ========== 
#define AT91C_MCI_PTCR  	0xFFFB4120 // PDC_MCI PDC Transfer Control Register
#define AT91C_MCI_TNPR  	0xFFFB4118 // PDC_MCI Transmit Next Pointer Register
#define AT91C_MCI_RNPR  	0xFFFB4110 // PDC_MCI Receive Next Pointer Register
#define AT91C_MCI_TPR   	0xFFFB4108 // PDC_MCI Transmit Pointer Register
#define AT91C_MCI_RPR   	0xFFFB4100 // PDC_MCI Receive Pointer Register
#define AT91C_MCI_PTSR  	0xFFFB4124 // PDC_MCI PDC Transfer Status Register
#define AT91C_MCI_TNCR  	0xFFFB411C // PDC_MCI Transmit Next Counter Register
#define AT91C_MCI_RNCR  	0xFFFB4114 // PDC_MCI Receive Next Counter Register
#define AT91C_MCI_TCR   	0xFFFB410C // PDC_MCI Transmit Counter Register
#define AT91C_MCI_RCR   	0xFFFB4104 // PDC_MCI Receive Counter Register
// ========== Register definition for MCI peripheral ========== 
#define AT91C_MCI_IDR   	0xFFFB4048 // MCI MCI Interrupt Disable Register
#define AT91C_MCI_SR    	0xFFFB4040 // MCI MCI Status Register
#define AT91C_MCI_RDR   	0xFFFB4030 // MCI MCI Receive Data Register
#define AT91C_MCI_RSPR  	0xFFFB4020 // MCI MCI Response Register
#define AT91C_MCI_ARGR  	0xFFFB4010 // MCI MCI Argument Register
#define AT91C_MCI_DTOR  	0xFFFB4008 // MCI MCI Data Timeout Register
#define AT91C_MCI_CR    	0xFFFB4000 // MCI MCI Control Register
#define AT91C_MCI_IMR   	0xFFFB404C // MCI MCI Interrupt Mask Register
#define AT91C_MCI_IER   	0xFFFB4044 // MCI MCI Interrupt Enable Register
#define AT91C_MCI_TDR   	0xFFFB4034 // MCI MCI Transmit Data Register
#define AT91C_MCI_CMDR  	0xFFFB4014 // MCI MCI Command Register
#define AT91C_MCI_SDCR  	0xFFFB400C // MCI MCI SD Card Register
#define AT91C_MCI_MR    	0xFFFB4004 // MCI MCI Mode Register
// ========== Register definition for UDP peripheral ========== 
#define AT91C_UDP_ISR   	0xFFFB001C // UDP Interrupt Status Register
#define AT91C_UDP_IDR   	0xFFFB0014 // UDP Interrupt Disable Register
#define AT91C_UDP_GLBSTATE 	0xFFFB0004 // UDP Global State Register
#define AT91C_UDP_FDR   	0xFFFB0050 // UDP Endpoint FIFO Data Register
#define AT91C_UDP_CSR   	0xFFFB0030 // UDP Endpoint Control and Status Register
#define AT91C_UDP_RSTEP 	0xFFFB0028 // UDP Reset Endpoint Register
#define AT91C_UDP_ICR   	0xFFFB0020 // UDP Interrupt Clear Register
#define AT91C_UDP_IMR   	0xFFFB0018 // UDP Interrupt Mask Register
#define AT91C_UDP_IER   	0xFFFB0010 // UDP Interrupt Enable Register
#define AT91C_UDP_FADDR 	0xFFFB0008 // UDP Function Address Register
#define AT91C_UDP_NUM   	0xFFFB0000 // UDP Frame Number Register
// ========== Register definition for TC5 peripheral ========== 
#define AT91C_TC5_CMR   	0xFFFA4084 // TC5 Channel Mode Register
#define AT91C_TC5_IDR   	0xFFFA40A8 // TC5 Interrupt Disable Register
#define AT91C_TC5_SR    	0xFFFA40A0 // TC5 Status Register
#define AT91C_TC5_RB    	0xFFFA4098 // TC5 Register B
#define AT91C_TC5_CV    	0xFFFA4090 // TC5 Counter Value
#define AT91C_TC5_CCR   	0xFFFA4080 // TC5 Channel Control Register
#define AT91C_TC5_IMR   	0xFFFA40AC // TC5 Interrupt Mask Register
#define AT91C_TC5_IER   	0xFFFA40A4 // TC5 Interrupt Enable Register
#define AT91C_TC5_RC    	0xFFFA409C // TC5 Register C
#define AT91C_TC5_RA    	0xFFFA4094 // TC5 Register A
// ========== Register definition for TC4 peripheral ========== 
#define AT91C_TC4_IMR   	0xFFFA406C // TC4 Interrupt Mask Register
#define AT91C_TC4_IER   	0xFFFA4064 // TC4 Interrupt Enable Register
#define AT91C_TC4_RC    	0xFFFA405C // TC4 Register C
#define AT91C_TC4_RA    	0xFFFA4054 // TC4 Register A
#define AT91C_TC4_CMR   	0xFFFA4044 // TC4 Channel Mode Register
#define AT91C_TC4_IDR   	0xFFFA4068 // TC4 Interrupt Disable Register
#define AT91C_TC4_SR    	0xFFFA4060 // TC4 Status Register
#define AT91C_TC4_RB    	0xFFFA4058 // TC4 Register B
#define AT91C_TC4_CV    	0xFFFA4050 // TC4 Counter Value
#define AT91C_TC4_CCR   	0xFFFA4040 // TC4 Channel Control Register
// ========== Register definition for TC3 peripheral ========== 
#define AT91C_TC3_IMR   	0xFFFA402C // TC3 Interrupt Mask Register
#define AT91C_TC3_CV    	0xFFFA4010 // TC3 Counter Value
#define AT91C_TC3_CCR   	0xFFFA4000 // TC3 Channel Control Register
#define AT91C_TC3_IER   	0xFFFA4024 // TC3 Interrupt Enable Register
#define AT91C_TC3_CMR   	0xFFFA4004 // TC3 Channel Mode Register
#define AT91C_TC3_RA    	0xFFFA4014 // TC3 Register A
#define AT91C_TC3_RC    	0xFFFA401C // TC3 Register C
#define AT91C_TC3_IDR   	0xFFFA4028 // TC3 Interrupt Disable Register
#define AT91C_TC3_RB    	0xFFFA4018 // TC3 Register B
#define AT91C_TC3_SR    	0xFFFA4020 // TC3 Status Register
// ========== Register definition for TCB1 peripheral ========== 
#define AT91C_TCB1_BCR  	0xFFFA4140 // TCB1 TC Block Control Register
#define AT91C_TCB1_BMR  	0xFFFA4144 // TCB1 TC Block Mode Register
// ========== Register definition for TC2 peripheral ========== 
#define AT91C_TC2_IMR   	0xFFFA00AC // TC2 Interrupt Mask Register
#define AT91C_TC2_IER   	0xFFFA00A4 // TC2 Interrupt Enable Register
#define AT91C_TC2_RC    	0xFFFA009C // TC2 Register C
#define AT91C_TC2_RA    	0xFFFA0094 // TC2 Register A
#define AT91C_TC2_CMR   	0xFFFA0084 // TC2 Channel Mode Register
#define AT91C_TC2_IDR   	0xFFFA00A8 // TC2 Interrupt Disable Register
#define AT91C_TC2_SR    	0xFFFA00A0 // TC2 Status Register
#define AT91C_TC2_RB    	0xFFFA0098 // TC2 Register B
#define AT91C_TC2_CV    	0xFFFA0090 // TC2 Counter Value
#define AT91C_TC2_CCR   	0xFFFA0080 // TC2 Channel Control Register
// ========== Register definition for TC1 peripheral ========== 
#define AT91C_TC1_IMR   	0xFFFA006C // TC1 Interrupt Mask Register
#define AT91C_TC1_IER   	0xFFFA0064 // TC1 Interrupt Enable Register
#define AT91C_TC1_RC    	0xFFFA005C // TC1 Register C
#define AT91C_TC1_RA    	0xFFFA0054 // TC1 Register A
#define AT91C_TC1_CMR   	0xFFFA0044 // TC1 Channel Mode Register
#define AT91C_TC1_IDR   	0xFFFA0068 // TC1 Interrupt Disable Register
#define AT91C_TC1_SR    	0xFFFA0060 // TC1 Status Register
#define AT91C_TC1_RB    	0xFFFA0058 // TC1 Register B
#define AT91C_TC1_CV    	0xFFFA0050 // TC1 Counter Value
#define AT91C_TC1_CCR   	0xFFFA0040 // TC1 Channel Control Register
// ========== Register definition for TC0 peripheral ========== 
#define AT91C_TC0_IMR   	0xFFFA002C // TC0 Interrupt Mask Register
#define AT91C_TC0_IER   	0xFFFA0024 // TC0 Interrupt Enable Register
#define AT91C_TC0_RC    	0xFFFA001C // TC0 Register C
#define AT91C_TC0_RA    	0xFFFA0014 // TC0 Register A
#define AT91C_TC0_CMR   	0xFFFA0004 // TC0 Channel Mode Register
#define AT91C_TC0_IDR   	0xFFFA0028 // TC0 Interrupt Disable Register
#define AT91C_TC0_SR    	0xFFFA0020 // TC0 Status Register
#define AT91C_TC0_RB    	0xFFFA0018 // TC0 Register B
#define AT91C_TC0_CV    	0xFFFA0010 // TC0 Counter Value
#define AT91C_TC0_CCR   	0xFFFA0000 // TC0 Channel Control Register
// ========== Register definition for TCB0 peripheral ========== 
#define AT91C_TCB0_BMR  	0xFFFA00C4 // TCB0 TC Block Mode Register
#define AT91C_TCB0_BCR  	0xFFFA00C0 // TCB0 TC Block Control Register
// ========== Register definition for UHP peripheral ========== 
#define AT91C_UHP_HcRhDescriptorA 	0x00300048 // UHP Root Hub characteristics A
#define AT91C_UHP_HcRhPortStatus 	0x00300054 // UHP Root Hub Port Status Register
#define AT91C_UHP_HcRhDescriptorB 	0x0030004C // UHP Root Hub characteristics B
#define AT91C_UHP_HcControl 	0x00300004 // UHP Operating modes for the Host Controller
#define AT91C_UHP_HcInterruptStatus 	0x0030000C // UHP Interrupt Status Register
#define AT91C_UHP_HcRhStatus 	0x00300050 // UHP Root Hub Status register
#define AT91C_UHP_HcRevision 	0x00300000 // UHP Revision
#define AT91C_UHP_HcCommandStatus 	0x00300008 // UHP Command & status Register
#define AT91C_UHP_HcInterruptEnable 	0x00300010 // UHP Interrupt Enable Register
#define AT91C_UHP_HcHCCA 	0x00300018 // UHP Pointer to the Host Controller Communication Area
#define AT91C_UHP_HcControlHeadED 	0x00300020 // UHP First Endpoint Descriptor of the Control list
#define AT91C_UHP_HcInterruptDisable 	0x00300014 // UHP Interrupt Disable Register
#define AT91C_UHP_HcPeriodCurrentED 	0x0030001C // UHP Current Isochronous or Interrupt Endpoint Descriptor
#define AT91C_UHP_HcControlCurrentED 	0x00300024 // UHP Endpoint Control and Status Register
#define AT91C_UHP_HcBulkCurrentED 	0x0030002C // UHP Current endpoint of the Bulk list
#define AT91C_UHP_HcFmInterval 	0x00300034 // UHP Bit time between 2 consecutive SOFs
#define AT91C_UHP_HcBulkHeadED 	0x00300028 // UHP First endpoint register of the Bulk list
#define AT91C_UHP_HcBulkDoneHead 	0x00300030 // UHP Last completed transfer descriptor
#define AT91C_UHP_HcFmRemaining 	0x00300038 // UHP Bit time remaining in the current Frame
#define AT91C_UHP_HcPeriodicStart 	0x00300040 // UHP Periodic Start
#define AT91C_UHP_HcLSThreshold 	0x00300044 // UHP LS Threshold
#define AT91C_UHP_HcFmNumber 	0x0030003C // UHP Frame number
// ========== Register definition for EMAC peripheral ========== 
#define AT91C_EMAC_RSR  	0xFFFBC020 // EMAC Receive Status Register
#define AT91C_EMAC_MAN  	0xFFFBC034 // EMAC PHY Maintenance Register
#define AT91C_EMAC_HSH  	0xFFFBC090 // EMAC Hash Address High[63:32]
#define AT91C_EMAC_MCOL 	0xFFFBC048 // EMAC Multiple Collision Frame Register
#define AT91C_EMAC_IER  	0xFFFBC028 // EMAC Interrupt Enable Register
#define AT91C_EMAC_SA2H 	0xFFFBC0A4 // EMAC Specific Address 2 High, Last 2 bytes
#define AT91C_EMAC_HSL  	0xFFFBC094 // EMAC Hash Address Low[31:0]
#define AT91C_EMAC_LCOL 	0xFFFBC05C // EMAC Late Collision Register
#define AT91C_EMAC_OK   	0xFFFBC04C // EMAC Frames Received OK Register
#define AT91C_EMAC_CFG  	0xFFFBC004 // EMAC Network Configuration Register
#define AT91C_EMAC_SA3L 	0xFFFBC0A8 // EMAC Specific Address 3 Low, First 4 bytes
#define AT91C_EMAC_SEQE 	0xFFFBC050 // EMAC Frame Check Sequence Error Register
#define AT91C_EMAC_ECOL 	0xFFFBC060 // EMAC Excessive Collision Register
#define AT91C_EMAC_ELR  	0xFFFBC070 // EMAC Excessive Length Error Register
#define AT91C_EMAC_SR   	0xFFFBC008 // EMAC Network Status Register
#define AT91C_EMAC_RBQP 	0xFFFBC018 // EMAC Receive Buffer Queue Pointer
#define AT91C_EMAC_CSE  	0xFFFBC064 // EMAC Carrier Sense Error Register
#define AT91C_EMAC_RJB  	0xFFFBC074 // EMAC Receive Jabber Register
#define AT91C_EMAC_USF  	0xFFFBC078 // EMAC Undersize Frame Register
#define AT91C_EMAC_IDR  	0xFFFBC02C // EMAC Interrupt Disable Register
#define AT91C_EMAC_SA1L 	0xFFFBC098 // EMAC Specific Address 1 Low, First 4 bytes
#define AT91C_EMAC_IMR  	0xFFFBC030 // EMAC Interrupt Mask Register
#define AT91C_EMAC_FRA  	0xFFFBC040 // EMAC Frames Transmitted OK Register
#define AT91C_EMAC_SA3H 	0xFFFBC0AC // EMAC Specific Address 3 High, Last 2 bytes
#define AT91C_EMAC_SA1H 	0xFFFBC09C // EMAC Specific Address 1 High, Last 2 bytes
#define AT91C_EMAC_SCOL 	0xFFFBC044 // EMAC Single Collision Frame Register
#define AT91C_EMAC_ALE  	0xFFFBC054 // EMAC Alignment Error Register
#define AT91C_EMAC_TAR  	0xFFFBC00C // EMAC Transmit Address Register
#define AT91C_EMAC_SA4L 	0xFFFBC0B0 // EMAC Specific Address 4 Low, First 4 bytes
#define AT91C_EMAC_SA2L 	0xFFFBC0A0 // EMAC Specific Address 2 Low, First 4 bytes
#define AT91C_EMAC_TUE  	0xFFFBC068 // EMAC Transmit Underrun Error Register
#define AT91C_EMAC_DTE  	0xFFFBC058 // EMAC Deferred Transmission Frame Register
#define AT91C_EMAC_TCR  	0xFFFBC010 // EMAC Transmit Control Register
#define AT91C_EMAC_CTL  	0xFFFBC000 // EMAC Network Control Register
#define AT91C_EMAC_SA4H 	0xFFFBC0B4 // EMAC Specific Address 4 High, Last 2 bytesr
#define AT91C_EMAC_CDE  	0xFFFBC06C // EMAC Code Error Register
#define AT91C_EMAC_SQEE 	0xFFFBC07C // EMAC SQE Test Error Register
#define AT91C_EMAC_TSR  	0xFFFBC014 // EMAC Transmit Status Register
#define AT91C_EMAC_DRFC 	0xFFFBC080 // EMAC Discarded RX Frame Register
// ========== Register definition for EBI peripheral ========== 
#define AT91C_EBI_CFGR  	0xFFFFFF64 // EBI Configuration Register
#define AT91C_EBI_CSA   	0xFFFFFF60 // EBI Chip Select Assignment Register
// ========== Register definition for SMC2 peripheral ========== 
#define AT91C_SMC2_CSR  	0xFFFFFF70 // SMC2 SMC2 Chip Select Register
// ========== Register definition for SDRC peripheral ========== 
#define AT91C_SDRC_IMR  	0xFFFFFFAC // SDRC SDRAM Controller Interrupt Mask Register
#define AT91C_SDRC_IER  	0xFFFFFFA4 // SDRC SDRAM Controller Interrupt Enable Register
#define AT91C_SDRC_SRR  	0xFFFFFF9C // SDRC SDRAM Controller Self Refresh Register
#define AT91C_SDRC_TR   	0xFFFFFF94 // SDRC SDRAM Controller Refresh Timer Register
#define AT91C_SDRC_ISR  	0xFFFFFFB0 // SDRC SDRAM Controller Interrupt Mask Register
#define AT91C_SDRC_IDR  	0xFFFFFFA8 // SDRC SDRAM Controller Interrupt Disable Register
#define AT91C_SDRC_LPR  	0xFFFFFFA0 // SDRC SDRAM Controller Low Power Register
#define AT91C_SDRC_CR   	0xFFFFFF98 // SDRC SDRAM Controller Configuration Register
#define AT91C_SDRC_MR   	0xFFFFFF90 // SDRC SDRAM Controller Mode Register
// ========== Register definition for BFC peripheral ========== 
#define AT91C_BFC_MR    	0xFFFFFFC0 // BFC BFC Mode Register








#ifdef __cplusplus
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#endif

#endif