at91rm9200.h

Vxworks下BSP源码

#define AT91C_DBGU_RCR  	0xFFFFF304 // PDC_DBGU Receive Counter Register
#define AT91C_DBGU_TCR  	0xFFFFF30C // PDC_DBGU Transmit Counter Register
#define AT91C_DBGU_RPR  	0xFFFFF300 // PDC_DBGU Receive Pointer Register
#define AT91C_DBGU_TPR  	0xFFFFF308 // PDC_DBGU Transmit Pointer Register
#define AT91C_DBGU_RNPR 	0xFFFFF310 // PDC_DBGU Receive Next Pointer Register
#define AT91C_DBGU_TNPR 	0xFFFFF318 // PDC_DBGU Transmit Next Pointer Register
// ========== Register definition for AIC peripheral ========== 
#define AT91C_AIC_ICCR  	0xFFFFF128 // AIC Interrupt Clear Command Register
#define AT91C_AIC_IECR  	0xFFFFF120 // AIC Interrupt Enable Command Register
#define AT91C_AIC_SMR   	0xFFFFF000 // AIC Source Mode Register
#define AT91C_AIC_ISCR  	0xFFFFF12C // AIC Interrupt Set Command Register
#define AT91C_AIC_EOICR 	0xFFFFF130 // AIC End of Interrupt Command Register
#define AT91C_AIC_DCR   	0xFFFFF138 // AIC Debug Control Register Protect
#define AT91C_AIC_FFER  	0xFFFFF140 // AIC Fast Forcing Enable Register
#define AT91C_AIC_SVR   	0xFFFFF080 // AIC Source Vector Register
#define AT91C_AIC_SPU   	0xFFFFF134 // AIC Spurious Vector Register
#define AT91C_AIC_FFDR  	0xFFFFF144 // AIC Fast Forcing Disable Register
#define AT91C_AIC_FVR   	0xFFFFF104 // AIC FIQ Vector Register
#define AT91C_AIC_FFSR  	0xFFFFF148 // AIC Fast Forcing Status Register
#define AT91C_AIC_IMR   	0xFFFFF110 // AIC Interrupt Mask Register
#define AT91C_AIC_ISR   	0xFFFFF108 // AIC Interrupt Status Register
#define AT91C_AIC_IVR   	0xFFFFF100 // AIC IRQ Vector Register
#define AT91C_AIC_IDCR  	0xFFFFF124 // AIC Interrupt Disable Command Register
#define AT91C_AIC_CISR  	0xFFFFF114 // AIC Core Interrupt Status Register
#define AT91C_AIC_IPR   	0xFFFFF10C // AIC Interrupt Pending Register
// ========== Register definition for PDC_SPI peripheral ========== 
#define AT91C_SPI_PTCR  	0xFFFE0120 // PDC_SPI PDC Transfer Control Register
#define AT91C_SPI_TNPR  	0xFFFE0118 // PDC_SPI Transmit Next Pointer Register
#define AT91C_SPI_RNPR  	0xFFFE0110 // PDC_SPI Receive Next Pointer Register
#define AT91C_SPI_TPR   	0xFFFE0108 // PDC_SPI Transmit Pointer Register
#define AT91C_SPI_RPR   	0xFFFE0100 // PDC_SPI Receive Pointer Register
#define AT91C_SPI_PTSR  	0xFFFE0124 // PDC_SPI PDC Transfer Status Register
#define AT91C_SPI_TNCR  	0xFFFE011C // PDC_SPI Transmit Next Counter Register
#define AT91C_SPI_RNCR  	0xFFFE0114 // PDC_SPI Receive Next Counter Register
#define AT91C_SPI_TCR   	0xFFFE010C // PDC_SPI Transmit Counter Register
#define AT91C_SPI_RCR   	0xFFFE0104 // PDC_SPI Receive Counter Register
// ========== Register definition for SPI peripheral ========== 
#define AT91C_SPI_CSR   	0xFFFE0030 // SPI Chip Select Register
#define AT91C_SPI_IDR   	0xFFFE0018 // SPI Interrupt Disable Register
#define AT91C_SPI_SR    	0xFFFE0010 // SPI Status Register
#define AT91C_SPI_RDR   	0xFFFE0008 // SPI Receive Data Register
#define AT91C_SPI_CR    	0xFFFE0000 // SPI Control Register
#define AT91C_SPI_IMR   	0xFFFE001C // SPI Interrupt Mask Register
#define AT91C_SPI_IER   	0xFFFE0014 // SPI Interrupt Enable Register
#define AT91C_SPI_TDR   	0xFFFE000C // SPI Transmit Data Register
#define AT91C_SPI_MR    	0xFFFE0004 // SPI Mode Register
// ========== Register definition for PDC_SSC2 peripheral ========== 
#define AT91C_SSC2_PTCR 	0xFFFD8120 // PDC_SSC2 PDC Transfer Control Register
#define AT91C_SSC2_TNPR 	0xFFFD8118 // PDC_SSC2 Transmit Next Pointer Register
#define AT91C_SSC2_RNPR 	0xFFFD8110 // PDC_SSC2 Receive Next Pointer Register
#define AT91C_SSC2_TPR  	0xFFFD8108 // PDC_SSC2 Transmit Pointer Register
#define AT91C_SSC2_RPR  	0xFFFD8100 // PDC_SSC2 Receive Pointer Register
#define AT91C_SSC2_PTSR 	0xFFFD8124 // PDC_SSC2 PDC Transfer Status Register
#define AT91C_SSC2_TNCR 	0xFFFD811C // PDC_SSC2 Transmit Next Counter Register
#define AT91C_SSC2_RNCR 	0xFFFD8114 // PDC_SSC2 Receive Next Counter Register
#define AT91C_SSC2_TCR  	0xFFFD810C // PDC_SSC2 Transmit Counter Register
#define AT91C_SSC2_RCR  	0xFFFD8104 // PDC_SSC2 Receive Counter Register
// ========== Register definition for SSC2 peripheral ========== 
#define AT91C_SSC2_IMR  	0xFFFD804C // SSC2 Interrupt Mask Register
#define AT91C_SSC2_IER  	0xFFFD8044 // SSC2 Interrupt Enable Register
#define AT91C_SSC2_RC1R 	0xFFFD803C // SSC2 Receive Compare 1 Register
#define AT91C_SSC2_TSHR 	0xFFFD8034 // SSC2 Transmit Sync Holding Register
#define AT91C_SSC2_CMR  	0xFFFD8004 // SSC2 Clock Mode Register
#define AT91C_SSC2_IDR  	0xFFFD8048 // SSC2 Interrupt Disable Register
#define AT91C_SSC2_TCMR 	0xFFFD8018 // SSC2 Transmit Clock Mode Register
#define AT91C_SSC2_RCMR 	0xFFFD8010 // SSC2 Receive Clock ModeRegister
#define AT91C_SSC2_CR   	0xFFFD8000 // SSC2 Control Register
#define AT91C_SSC2_RFMR 	0xFFFD8014 // SSC2 Receive Frame Mode Register
#define AT91C_SSC2_TFMR 	0xFFFD801C // SSC2 Transmit Frame Mode Register
#define AT91C_SSC2_THR  	0xFFFD8024 // SSC2 Transmit Holding Register
#define AT91C_SSC2_SR   	0xFFFD8040 // SSC2 Status Register
#define AT91C_SSC2_RC0R 	0xFFFD8038 // SSC2 Receive Compare 0 Register
#define AT91C_SSC2_RSHR 	0xFFFD8030 // SSC2 Receive Sync Holding Register
#define AT91C_SSC2_RHR  	0xFFFD8020 // SSC2 Receive Holding Register
// ========== Register definition for PDC_SSC1 peripheral ========== 
#define AT91C_SSC1_PTCR 	0xFFFD4120 // PDC_SSC1 PDC Transfer Control Register
#define AT91C_SSC1_TNPR 	0xFFFD4118 // PDC_SSC1 Transmit Next Pointer Register
#define AT91C_SSC1_RNPR 	0xFFFD4110 // PDC_SSC1 Receive Next Pointer Register
#define AT91C_SSC1_TPR  	0xFFFD4108 // PDC_SSC1 Transmit Pointer Register
#define AT91C_SSC1_RPR  	0xFFFD4100 // PDC_SSC1 Receive Pointer Register
#define AT91C_SSC1_PTSR 	0xFFFD4124 // PDC_SSC1 PDC Transfer Status Register
#define AT91C_SSC1_TNCR 	0xFFFD411C // PDC_SSC1 Transmit Next Counter Register
#define AT91C_SSC1_RNCR 	0xFFFD4114 // PDC_SSC1 Receive Next Counter Register
#define AT91C_SSC1_TCR  	0xFFFD410C // PDC_SSC1 Transmit Counter Register
#define AT91C_SSC1_RCR  	0xFFFD4104 // PDC_SSC1 Receive Counter Register
// ========== Register definition for SSC1 peripheral ========== 
#define AT91C_SSC1_RFMR 	0xFFFD4014 // SSC1 Receive Frame Mode Register
#define AT91C_SSC1_CMR  	0xFFFD4004 // SSC1 Clock Mode Register
#define AT91C_SSC1_IDR  	0xFFFD4048 // SSC1 Interrupt Disable Register
#define AT91C_SSC1_SR   	0xFFFD4040 // SSC1 Status Register
#define AT91C_SSC1_RC0R 	0xFFFD4038 // SSC1 Receive Compare 0 Register
#define AT91C_SSC1_RSHR 	0xFFFD4030 // SSC1 Receive Sync Holding Register
#define AT91C_SSC1_RHR  	0xFFFD4020 // SSC1 Receive Holding Register
#define AT91C_SSC1_TCMR 	0xFFFD4018 // SSC1 Transmit Clock Mode Register
#define AT91C_SSC1_RCMR 	0xFFFD4010 // SSC1 Receive Clock ModeRegister
#define AT91C_SSC1_CR   	0xFFFD4000 // SSC1 Control Register
#define AT91C_SSC1_IMR  	0xFFFD404C // SSC1 Interrupt Mask Register
#define AT91C_SSC1_IER  	0xFFFD4044 // SSC1 Interrupt Enable Register
#define AT91C_SSC1_RC1R 	0xFFFD403C // SSC1 Receive Compare 1 Register
#define AT91C_SSC1_TSHR 	0xFFFD4034 // SSC1 Transmit Sync Holding Register
#define AT91C_SSC1_THR  	0xFFFD4024 // SSC1 Transmit Holding Register
#define AT91C_SSC1_TFMR 	0xFFFD401C // SSC1 Transmit Frame Mode Register
// ========== Register definition for PDC_SSC0 peripheral ========== 
#define AT91C_SSC0_PTCR 	0xFFFD0120 // PDC_SSC0 PDC Transfer Control Register
#define AT91C_SSC0_TNPR 	0xFFFD0118 // PDC_SSC0 Transmit Next Pointer Register
#define AT91C_SSC0_RNPR 	0xFFFD0110 // PDC_SSC0 Receive Next Pointer Register
#define AT91C_SSC0_TPR  	0xFFFD0108 // PDC_SSC0 Transmit Pointer Register
#define AT91C_SSC0_RPR  	0xFFFD0100 // PDC_SSC0 Receive Pointer Register
#define AT91C_SSC0_PTSR 	0xFFFD0124 // PDC_SSC0 PDC Transfer Status Register
#define AT91C_SSC0_TNCR 	0xFFFD011C // PDC_SSC0 Transmit Next Counter Register
#define AT91C_SSC0_RNCR 	0xFFFD0114 // PDC_SSC0 Receive Next Counter Register
#define AT91C_SSC0_TCR  	0xFFFD010C // PDC_SSC0 Transmit Counter Register
#define AT91C_SSC0_RCR  	0xFFFD0104 // PDC_SSC0 Receive Counter Register
// ========== Register definition for SSC0 peripheral ========== 
#define AT91C_SSC0_IMR  	0xFFFD004C // SSC0 Interrupt Mask Register
#define AT91C_SSC0_IER  	0xFFFD0044 // SSC0 Interrupt Enable Register
#define AT91C_SSC0_RC1R 	0xFFFD003C // SSC0 Receive Compare 1 Register
#define AT91C_SSC0_TSHR 	0xFFFD0034 // SSC0 Transmit Sync Holding Register
#define AT91C_SSC0_THR  	0xFFFD0024 // SSC0 Transmit Holding Register
#define AT91C_SSC0_TFMR 	0xFFFD001C // SSC0 Transmit Frame Mode Register
#define AT91C_SSC0_RFMR 	0xFFFD0014 // SSC0 Receive Frame Mode Register
#define AT91C_SSC0_CMR  	0xFFFD0004 // SSC0 Clock Mode Register
#define AT91C_SSC0_IDR  	0xFFFD0048 // SSC0 Interrupt Disable Register
#define AT91C_SSC0_SR   	0xFFFD0040 // SSC0 Status Register
#define AT91C_SSC0_RC0R 	0xFFFD0038 // SSC0 Receive Compare 0 Register
#define AT91C_SSC0_RSHR 	0xFFFD0030 // SSC0 Receive Sync Holding Register
#define AT91C_SSC0_RHR  	0xFFFD0020 // SSC0 Receive Holding Register
#define AT91C_SSC0_TCMR 	0xFFFD0018 // SSC0 Transmit Clock Mode Register
#define AT91C_SSC0_RCMR 	0xFFFD0010 // SSC0 Receive Clock ModeRegister
#define AT91C_SSC0_CR   	0xFFFD0000 // SSC0 Control Register
// ========== Register definition for PDC_US3 peripheral ========== 
#define AT91C_US3_PTSR  	0xFFFCC124 // PDC_US3 PDC Transfer Status Register
#define AT91C_US3_TNCR  	0xFFFCC11C // PDC_US3 Transmit Next Counter Register
#define AT91C_US3_RNCR  	0xFFFCC114 // PDC_US3 Receive Next Counter Register
#define AT91C_US3_TCR   	0xFFFCC10C // PDC_US3 Transmit Counter Register
#define AT91C_US3_RCR   	0xFFFCC104 // PDC_US3 Receive Counter Register
#define AT91C_US3_PTCR  	0xFFFCC120 // PDC_US3 PDC Transfer Control Register
#define AT91C_US3_TNPR  	0xFFFCC118 // PDC_US3 Transmit Next Pointer Register
#define AT91C_US3_RNPR  	0xFFFCC110 // PDC_US3 Receive Next Pointer Register
#define AT91C_US3_TPR   	0xFFFCC108 // PDC_US3 Transmit Pointer Register
#define AT91C_US3_RPR   	0xFFFCC100 // PDC_US3 Receive Pointer Register
// ========== Register definition for US3 peripheral ========== 
#define AT91C_US3_IF    	0xFFFCC04C // US3 IRDA_FILTER Register
#define AT91C_US3_NER   	0xFFFCC044 // US3 Nb Errors Register
#define AT91C_US3_RTOR  	0xFFFCC024 // US3 Receiver Time-out Register
#define AT91C_US3_THR   	0xFFFCC01C // US3 Transmitter Holding Register
#define AT91C_US3_CSR   	0xFFFCC014 // US3 Channel Status Register
#define AT91C_US3_IDR   	0xFFFCC00C // US3 Interrupt Disable Register
#define AT91C_US3_MR    	0xFFFCC004 // US3 Mode Register
#define AT91C_US3_XXR   	0xFFFCC048 // US3 XON_XOFF Register
#define AT91C_US3_FIDI  	0xFFFCC040 // US3 FI_DI_Ratio Register
#define AT91C_US3_TTGR  	0xFFFCC028 // US3 Transmitter Time-guard Register
#define AT91C_US3_BRGR  	0xFFFCC020 // US3 Baud Rate Generator Register
#define AT91C_US3_RHR   	0xFFFCC018 // US3 Receiver Holding Register
#define AT91C_US3_IMR   	0xFFFCC010 // US3 Interrupt Mask Register
#define AT91C_US3_IER   	0xFFFCC008 // US3 Interrupt Enable Register
#define AT91C_US3_CR    	0xFFFCC000 // US3 Control Register
// ========== Register definition for PDC_US2 peripheral ========== 
#define AT91C_US2_PTSR  	0xFFFC8124 // PDC_US2 PDC Transfer Status Register
#define AT91C_US2_TNCR  	0xFFFC811C // PDC_US2 Transmit Next Counter Register
#define AT91C_US2_RNCR  	0xFFFC8114 // PDC_US2 Receive Next Counter Register
#define AT91C_US2_TCR   	0xFFFC810C // PDC_US2 Transmit Counter Register
#define AT91C_US2_PTCR  	0xFFFC8120 // PDC_US2 PDC Transfer Control Register
#define AT91C_US2_RCR   	0xFFFC8104 // PDC_US2 Receive Counter Register
#define AT91C_US2_TNPR  	0xFFFC8118 // PDC_US2 Transmit Next Pointer Register
#define AT91C_US2_RPR   	0xFFFC8100 // PDC_US2 Receive Pointer Register
#define AT91C_US2_TPR   	0xFFFC8108 // PDC_US2 Transmit Pointer Register
#define AT91C_US2_RNPR  	0xFFFC8110 // PDC_US2 Receive Next Pointer Register
// ========== Register definition for US2 peripheral ========== 
#define AT91C_US2_XXR   	0xFFFC8048 // US2 XON_XOFF Register
#define AT91C_US2_FIDI  	0xFFFC8040 // US2 FI_DI_Ratio Register
#define AT91C_US2_TTGR  	0xFFFC8028 // US2 Transmitter Time-guard Register
#define AT91C_US2_BRGR  	0xFFFC8020 // US2 Baud Rate Generator Register
#define AT91C_US2_RHR   	0xFFFC8018 // US2 Receiver Holding Register
#define AT91C_US2_IMR   	0xFFFC8010 // US2 Interrupt Mask Register
#define AT91C_US2_IER   	0xFFFC8008 // US2 Interrupt Enable Register
#define AT91C_US2_CR    	0xFFFC8000 // US2 Control Register
#define AT91C_US2_IF    	0xFFFC804C // US2 IRDA_FILTER Register
#define AT91C_US2_NER   	0xFFFC8044 // US2 Nb Errors Register
#define AT91C_US2_RTOR  	0xFFFC8024 // US2 Receiver Time-out Register
#define AT91C_US2_THR   	0xFFFC801C // US2 Transmitter Holding Register
#define AT91C_US2_CSR   	0xFFFC8014 // US2 Channel Status Register
#define AT91C_US2_IDR   	0xFFFC800C // US2 Interrupt Disable Register
#define AT91C_US2_MR    	0xFFFC8004 // US2 Mode Register
// ========== Register definition for PDC_US1 peripheral ========== 
#define AT91C_US1_PTSR  	0xFFFC4124 // PDC_US1 PDC Transfer Status Register
#define AT91C_US1_TNCR  	0xFFFC411C // PDC_US1 Transmit Next Counter Register
#define AT91C_US1_RNCR  	0xFFFC4114 // PDC_US1 Receive Next Counter Register
#define AT91C_US1_TCR   	0xFFFC410C // PDC_US1 Transmit Counter Register
#define AT91C_US1_RCR   	0xFFFC4104 // PDC_US1 Receive Counter Register
#define AT91C_US1_PTCR  	0xFFFC4120 // PDC_US1 PDC Transfer Control Register
#define AT91C_US1_TNPR  	0xFFFC4118 // PDC_US1 Transmit Next Pointer Register
#define AT91C_US1_RNPR  	0xFFFC4110 // PDC_US1 Receive Next Pointer Register
#define AT91C_US1_TPR   	0xFFFC4108 // PDC_US1 Transmit Pointer Register
#define AT91C_US1_RPR   	0xFFFC4100 // PDC_US1 Receive Pointer Register
// ========== Register definition for US1 peripheral ========== 
#define AT91C_US1_XXR   	0xFFFC4048 // US1 XON_XOFF Register
#define AT91C_US1_RHR   	0xFFFC4018 // US1 Receiver Holding Register
#define AT91C_US1_IMR   	0xFFFC4010 // US1 Interrupt Mask Register
#define AT91C_US1_IER   	0xFFFC4008 // US1 Interrupt Enable Register
#define AT91C_US1_CR    	0xFFFC4000 // US1 Control Register
#define AT91C_US1_RTOR  	0xFFFC4024 // US1 Receiver Time-out Register
#define AT91C_US1_THR   	0xFFFC401C // US1 Transmitter Holding Register
#define AT91C_US1_CSR   	0xFFFC4014 // US1 Channel Status Register
#define AT91C_US1_IDR   	0xFFFC400C // US1 Interrupt Disable Register
#define AT91C_US1_FIDI  	0xFFFC4040 // US1 FI_DI_Ratio Register
#define AT91C_US1_BRGR  	0xFFFC4020 // US1 Baud Rate Generator Register
#define AT91C_US1_TTGR  	0xFFFC4028 // US1 Transmitter Time-guard Register
#define AT91C_US1_IF    	0xFFFC404C // US1 IRDA_FILTER Register
#define AT91C_US1_NER   	0xFFFC4044 // US1 Nb Errors Register
#define AT91C_US1_MR    	0xFFFC4004 // US1 Mode Register
// ========== Register definition for PDC_US0 peripheral ========== 
#define AT91C_US0_PTCR  	0xFFFC0120 // PDC_US0 PDC Transfer Control Register
#define AT91C_US0_TNPR  	0xFFFC0118 // PDC_US0 Transmit Next Pointer Register
#define AT91C_US0_RNPR  	0xFFFC0110 // PDC_US0 Receive Next Pointer Register
#define AT91C_US0_TPR   	0xFFFC0108 // PDC_US0 Transmit Pointer Register
#define AT91C_US0_RPR   	0xFFFC0100 // PDC_US0 Receive Pointer Register
#define AT91C_US0_PTSR  	0xFFFC0124 // PDC_US0 PDC Transfer Status Register
#define AT91C_US0_TNCR  	0xFFFC011C // PDC_US0 Transmit Next Counter Register
#define AT91C_US0_RNCR  	0xFFFC0114 // PDC_US0 Receive Next Counter Register
#define AT91C_US0_TCR   	0xFFFC010C // PDC_US0 Transmit Counter Register
#define AT91C_US0_RCR   	0xFFFC0104 // PDC_US0 Receive Counter Register
// ========== Register definition for US0 peripheral ========== 
#define AT91C_US0_TTGR  	0xFFFC0028 // US0 Transmitter Time-guard Register
#define AT91C_US0_BRGR  	0xFFFC0020 // US0 Baud Rate Generator Register
#define AT91C_US0_RHR   	0xFFFC0018 // US0 Receiver Holding Register
#define AT91C_US0_IMR   	0xFFFC0010 // US0 Interrupt Mask Register