wrsbcarm7.h

Vxworks下BSP源码

/* sbcarm7.h - WindRiver SBC ARM7 header file */


/* Copyright 1984-2001 Wind River Systems, Inc. */
#include "copyright_wrs.h"

/*
modification history
--------------------
01f,16jul02,m_h  C++ protection
01e,04jan02,m_h  minor cleanup
01d,03dec01,m_h  remove Diab warnings
01c,27sep01,m_h  base MAC address on user DIP setting
01b,22may01,m_h  documentation
01a,12apr01,m_h  created from snds100 template.
*/

/*
This file contains I/O address and related constants for the SBC ARM7 board.
*/

#ifndef    INCsbcarm7h
#define    INCsbcarm7h

#ifdef __cplusplus
extern "C" {
#endif

#include "sngks32c.h"

#define TARGET_ATARM920T





/* interrupt levels */


#define INT_LVL_FIQ         0    /* FIQ */
#define INT_LVL_SYSIRQ      1    /* System Interrupt */
#define INT_LVL_PIOA        2    /* Parallel I/O Controller A interrupt */
#define INT_LVL_PIOB        3    /* Parallel I/O Controller B interrupt */
#define INT_LVL_PIOC        4    /* Parallel I/O Controller C interrupt */
#define INT_LVL_PIOD        5    /* Parallel I/O Controller D interrupt */
#define INT_LVL_US0	        6    /* USART 0 interrupt */
#define INT_LVL_US1 	    7    /* USART 1 interrupt */
#define INT_LVL_US2         8    /* USART 2 interrupt */
#define INT_LVL_US3         9    /* USART 3 interrupt */
#define INT_LVL_MIC        10    /* Multimedia Card Interface interrupt */
#define INT_LVL_UDP        11    /* USB Device Port  interrupt */
#define INT_LVL_TWI        12    /* Two-wire Interface interrupt */
#define INT_LVL_SPI        13    /* Serial Peripheral Interface interrupt */
#define INT_LVL_SSC0       14    /* Synchronous Serial Controller 0 interrupt */
#define INT_LVL_SSC1       15    /* Synchronous Serial Controller 1 interrupt */
#define INT_LVL_SSC2       16    /* Synchronous Serial Controller 2 interrupt */
#define INT_LVL_TC0        17    /* Timer/Counter 0 interrupt */
#define INT_LVL_TC1        18    /* Timer/Counter 1 interrupt */
#define INT_LVL_TC2        19    /* Timer/Counter 2 interrupt */
#define INT_LVL_TC3        20    /* Timer/Counter 3 interrupt */
#define INT_LVL_TC4        21    /* Timer/Counter 4 interrupt */
#define INT_LVL_TC5        22    /* Timer/Counter 5 interrupt */
#define INT_LVL_UHP 	   23	 /* USB Host Port interrupt */
#define INT_LVL_EMAC 	   24    /* Ethernet MAC interrupt */
#define INT_LVL_IRQ0	   25	 /* Advanced Interrupt Controller interrupt */
#define INT_LVL_IRQ1       26    /* Advanced Interrupt Controller interrupt */
#define INT_LVL_IRQ2       27    /* Advanced Interrupt Controller interrupt */
#define INT_LVL_IRQ3       28    /* Advanced Interrupt Controller interrupt */
#define INT_LVL_IRQ4	   29	 /* Advanced Interrupt Controller interrupt */
#define INT_LVL_IRQ5       30    /* Advanced Interrupt Controller interrupt */
#define INT_LVL_IRQ6       31    /* Advanced Interrupt Controller interrupt */



/* interrupt vectors */


#define INT_VEC_FIQ         IVEC_TO_INUM(INT_LVL_FIQ)    /* FIQ */
#define INT_VEC_SYSIRQ      IVEC_TO_INUM(INT_LVL_SYSIRQ)    /* System Interrupt */
#define INT_VEC_PIOA        IVEC_TO_INUM(INT_LVL_PIOA)    /* Parallel I/O Controller A interrupt */
#define INT_VEC_PIOB        IVEC_TO_INUM(INT_LVL_PIOB)    /* Parallel I/O Controller B interrupt */
#define INT_VEC_PIOC        IVEC_TO_INUM(INT_LVL_PIOC)    /* Parallel I/O Controller C interrupt */
#define INT_VEC_PIOD        IVEC_TO_INUM(INT_LVL_PIOD)    /* Parallel I/O Controller D interrupt */
#define INT_VEC_US0	        IVEC_TO_INUM(INT_LVL_US0)    /* USART 0 interrupt */
#define INT_VEC_US1 	    IVEC_TO_INUM(INT_LVL_US1)    /* USART 1 interrupt */
#define INT_VEC_US2         IVEC_TO_INUM(INT_LVL_US2)    /* USART 2 interrupt */
#define INT_VEC_US3         IVEC_TO_INUM(INT_LVL_US3)    /* USART 3 interrupt */
#define INT_VEC_MIC         IVEC_TO_INUM(INT_LVL_MIC)    /* Multimedia Card Interface interrupt */
#define INT_VEC_UDP         IVEC_TO_INUM(INT_LVL_UDP)    /* USB Device Port  interrupt */
#define INT_VEC_TWI         IVEC_TO_INUM(INT_LVL_TWI)    /* Two-wire Interface interrupt */
#define INT_VEC_SPI         IVEC_TO_INUM(INT_LVL_SPI)    /* Serial Peripheral Interface interrupt */
#define INT_VEC_SSC0        IVEC_TO_INUM(INT_LVL_SSC0)    /* Synchronous Serial Controller 0 interrupt */
#define INT_VEC_SSC1        IVEC_TO_INUM(INT_LVL_SSC1)    /* Synchronous Serial Controller 1 interrupt */
#define INT_VEC_SSC2        IVEC_TO_INUM(INT_LVL_SSC2)    /* Synchronous Serial Controller 2 interrupt */
#define INT_VEC_TC0         IVEC_TO_INUM(INT_LVL_TC0)    /* Timer/Counter 0 interrupt */
#define INT_VEC_TC1         IVEC_TO_INUM(INT_LVL_TC1)    /* Timer/Counter 1 interrupt */
#define INT_VEC_TC2         IVEC_TO_INUM(INT_LVL_TC2)    /* Timer/Counter 2 interrupt */
#define INT_VEC_TC3         IVEC_TO_INUM(INT_LVL_TC3)    /* Timer/Counter 3 interrupt */
#define INT_VEC_TC4         IVEC_TO_INUM(INT_LVL_TC4)    /* Timer/Counter 4 interrupt */
#define INT_VEC_TC5         IVEC_TO_INUM(INT_LVL_TC5)    /* Timer/Counter 5 interrupt */
#define INT_VEC_UHP 	    IVEC_TO_INUM(INT_LVL_UHP)	 /* USB Host Port interrupt */
#define INT_VEC_EMAC 	    IVEC_TO_INUM(INT_LVL_EMAC)    /* Ethernet MAC interrupt */
#define INT_VEC_IRQ0	    IVEC_TO_INUM(INT_LVL_IRQ0)	 /* Advanced Interrupt Controller interrupt */
#define INT_VEC_IRQ1        IVEC_TO_INUM(INT_LVL_IRQ1)    /* Advanced Interrupt Controller interrupt */
#define INT_VEC_IRQ2        IVEC_TO_INUM(INT_LVL_IRQ2)    /* Advanced Interrupt Controller interrupt */
#define INT_VEC_IRQ3        IVEC_TO_INUM(INT_LVL_IRQ3)    /* Advanced Interrupt Controller interrupt */
#define INT_VEC_IRQ4	    IVEC_TO_INUM(INT_LVL_IRQ4)	 /* Advanced Interrupt Controller interrupt */
#define INT_VEC_IRQ5        IVEC_TO_INUM(INT_LVL_IRQ5)    /* Advanced Interrupt Controller interrupt */
#define INT_VEC_IRQ6        IVEC_TO_INUM(INT_LVL_IRQ6)    /* Advanced Interrupt Controller interrupt */






#define N_ATARM920T_UART_CHANNELS	2	/*  1 DBGU channel and 1 USART channel  are used , 3 USART channels are reserved */
#define N_SIO_CHANNELS          N_ATARM920T_UART_CHANNELS
#define N_UART_CHANNELS         N_ATARM920T_UART_CHANNELS
#define UART_REG_ADDR_INTERVAL  1        /* registers 4 bytes apart */












#define TARGET_SBCARM7


#define SBCARM7_FLASH_BASE 0x1000000


/*
 * Local-to-Bus memory address constants:
 * the local memory address always appears at 0 locally;
 * it is not dual ported.
 */

#define LOCAL_MEM_LOCAL_ADRS  0x20000000    /* fixed */
#define LOCAL_MEM_BUS_ADRS    0x00000000    /* fixed */


#define BUS                   BUS_TYPE_NONE


#define SBCARM7_CPU_SPEED         50000000    /* CPU clocked at 50 MHz. The timer */
                    /* speed is related to this */


/* definitions for the KS32C50100 UART */
#if 0
#define N_SBCARM7_UART_CHANNELS     2        /* number of SBCARM7 UART chans */
#define N_SIO_CHANNELS          N_SBCARM7_UART_CHANNELS
#define N_UART_CHANNELS         N_SBCARM7_UART_CHANNELS
#define UART_REG_ADDR_INTERVAL  1        /* registers 4 bytes apart */
#endif

/* LED Registers (write) */
#define  SBCARM7_LEDREG             0x3fd4000

/* USER DIP switch (read) */
#define  SBCARM7_USERREG            0x3fd4000
#define READ_USERDIP()              (*((volatile char *)SBCARM7_USERREG) & 0xff)

/*************************************************************************
 *
 * DRAM Memory Bank 0 area MAP for Exception vector table 
 * and Stack, User code area. 
 *
 */

#define DRAM_BASE           0x0          /* Final start address of DRAM */
#define DRAM_LIMIT          0x400000
#define RESET_DRAM_START    0x1000000    /* Start of DRAM on power-up */
#define RESET_ROM_START     0x0          /* Start of ROM on power-up */

/****************************************************************************
 *
 * Format of the Program Status Register 
 */

#define FBit         0x40
#define IBit         0x80
#define LOCKOUT      0xC0     /* Interrupt lockout value */
#define LOCK_MSK     0xC0     /* Interrupt lockout mask value */
#define MODE_MASK    0x1F     /* Processor Mode Mask */
#define UDF_MODE     0x1B     /* Undefine Mode(UDF) */
#define ABT_MODE     0x17     /* Abort Mode(ABT) */
#define SUP_MODE     0x13     /* Supervisor Mode (SVC) */
#define IRQ_MODE     0x12     /* Interrupt Mode (IRQ) */
#define FIQ_MODE     0x11     /* Fast Interrupt Mode (FIQ) */
#define USR_MODE     0x10     /* User Mode(USR) */

/*************************************************************************
 * SYSTEM CLOCK 
 */

#define MHz            1000000
#define fMCLK_MHz      50000000     /* 50MHz, KS32C50100*/
#define fMCLK          50           /* fMCLK_MHz/MHz */

/*************************************************************************
 * SYSTEM MEMORY CONTROL REGISTER EQU TABLES 
 */

/* SYSCFG Register Value */
#define SYSCONFIG_VAL           0x07ffffa0    /* System Configuration Value, EDO RAM */
#define SYSCONFIG_VAL_SDRAM     0x87ffffa0    /* System Configuration Value, SDRAM */

/* CLKCON Clock configuration register Values */
#define tCDIV           (0<<0)
#define tWE             (0<<16)
#define tMUX            (0<<17)
#define tAC             (0<<18)
#define tTEST           (0<<31)


#define rCLKCON    (tCDIV+tWE+tMUX+tAC+tTEST)

/* EXTACONx External I/O access timing register Values */
#define tCOS0           (1<<0)
#define tACS0           (1<<3)
#define tCOH0           (1<<6)
#define tACC0           (1<<9)
#define tCOS1           (1<<16)
#define tACS1           (1<<19)
#define tCOH1           (1<<22)
#define tACC1           (1<<25)

#define rEXTACON0    (tCOS0+tACS0+tCOH0+tACC0+tCOS1+tACS1+tCOH1+tACC1)

#define tCOS2           (7<<0)
#define tACS2           (7<<3)
#define tCOH2           (7<<6)
#define tACC2           (7<<9)
#define tCOS3           (7<<16)
#define tACS3           (7<<19)
#define tCOH3           (7<<22)
#define tACC3           (7<<25)

#define rEXTACON1    (tCOS2+tACS2+tCOH2+tACC2+tCOS3+tACS3+tCOH3+tACC3)

/***********************************************************
 *
 * -> EXTDBWTH : Memory Bus Width register
 */
#define DSR0  (3<<0)     /* ROM0, 0 : Disable, 1 : Byte etc.*/
#define DSR1  (1<<2)     /* ROM1  */
#define DSR2  (1<<4)     /* ROM2  */
#define DSR3  (0<<6)     /* ROM3  */
#define DSR4  (0<<8)     /* ROM4  */
#define DSR5  (0<<10)    /* ROM5  */
#define DSD0  (3<<12)    /* DRAM0 */
#define DSD1  (0<<14)    /* DRAM1 */
#define DSD2  (0<<16)    /* DRAM2 */
#define DSD3  (0<<18)    /* DRAM3 */
#define DSX0  (0<<20)    /* EXTIO0*/
#define DSX1  (1<<22)    /* EXTIO1*/
#define DSX2  (1<<24)    /* EXTIO2*/
#define DSX3  (1<<26)    /* EXTIO3*/

#define rEXTDBWTH     (DSR0+DSR1+DSR2+DSR3+DSR4+DSR5+DSD0+DSD1+DSD2+DSD3+DSX0+DSX1+DSX2+DSX3)