sngks32c.h

Vxworks下BSP源码

/* sngks32c.h - header for Samsung ks32c with ARM7 core */

/* Copyright 1984-2001 Wind River Systems, Inc. */
#include "copyright_wrs.h"

/*
modification history
--------------------
01a,12apr01,m_h  created from snds100 template.
*/

#ifndef __INCsngks32ch
#define __INCsngks32ch

#ifdef __cplusplus
extern "C" {
#endif




#define AT91C_INTNUMLEVELS		32



/*************************************************************************
*Register definition for AIC peripheral 
*
*/


#define AT91C_AIC_ICCR  	0xFFFFF128 /* AIC Interrupt Clear Command Register */
#define AT91C_AIC_IECR  	0xFFFFF120 /* AIC Interrupt Enable Command Register */
#define AT91C_AIC_SMR   	0xFFFFF000 /* AIC Source Mode Register */
#define AT91C_AIC_ISCR  	0xFFFFF12C /* AIC Interrupt Set Command Register */

#define AT91C_AIC_EOICR 	0xFFFFF130 /* AIC End of Interrupt Command Register */
#define AT91C_AIC_DCR   	0xFFFFF138 /* AIC Debug Control Register  Protect */
#define AT91C_AIC_FFER  	0xFFFFF140 /* AIC Fast Forcing Enable Register */
#define AT91C_AIC_SVR   	0xFFFFF080 /* AIC Source Vector Register */

#define AT91C_AIC_SPU   	0xFFFFF134 /* AIC Spurious Vector Register */
#define AT91C_AIC_FFDR  	0xFFFFF144 /* AIC Fast Forcing Disable Register */
#define AT91C_AIC_FVR   	0xFFFFF104 /* AIC FIQ Vector Register */
#define AT91C_AIC_FFSR  	0xFFFFF148 /* AIC Fast Forcing Status Register */

#define AT91C_AIC_IMR   	0xFFFFF110 /* AIC Interrupt Mask Register */
#define AT91C_AIC_ISR   	0xFFFFF108 /* AIC Interrupt Status Register */
#define AT91C_AIC_IVR   	0xFFFFF100 /* AIC IRQ Vector Register */
#define AT91C_AIC_IDCR  	0xFFFFF124 /* AIC Interrupt Disable Command Register */
#define AT91C_AIC_CISR  	0xFFFFF114 /* AIC Core Interrupt Status Register */
#define AT91C_AIC_IPR   	0xFFFFF10C /* AIC Interrupt Pending Register */






/* register base address definnition for DBGU and USART */

#define AT91C_DBGU_BASE_ADR		0xFFFFF200
#define AT91C_US0_BASE_ADR 	0xFFFC0000
#define AT91C_US1_BASE_ADR 	0xFFFC4000
#define AT91C_US2_BASE_ADR 	0xFFFC8000
#define AT91C_US3_BASE_ADR 	0xFFFCC000



#define AT91C_PIOA_BASE_ADR	0xFFFFF400
#define AT91C_PIOB_BASE_ADR	0xFFFFF600
#define AT91C_PIOC_BASE_ADR	0xFFFFF800
#define AT91C_PIOD_BASE_ADR	0xFFFFFA00









#if 0

/*************************************************************************
* KS32C50100 SPECIAL REGISTERS 
*
*/

#define ASIC_BASE          0x3ff0000

/* Interrupt Control */

#define INT_CNTRL_BASE     (ASIC_BASE+0x4000) /*Define base of all interrupt */

/*SYSTEM MANAGER REGISTERS */

#define SNGKS32C_SYSCFG        (ASIC_BASE+0x0000)
#define SNGKS32C_CLKCON        (ASIC_BASE+0x3000)
#define SNGKS32C_EXTACON0      (ASIC_BASE+0x3008)
#define SNGKS32C_EXTACON1      (ASIC_BASE+0x300c)
#define SNGKS32C_EXTDBWTH      (ASIC_BASE+0x3010)
#define SNGKS32C_ROMCON0       (ASIC_BASE+0x3014)
#define SNGKS32C_ROMCON1       (ASIC_BASE+0x3018)
#define SNGKS32C_ROMCON2       (ASIC_BASE+0x301c)
#define SNGKS32C_ROMCON3       (ASIC_BASE+0x3020)
#define SNGKS32C_ROMCON4       (ASIC_BASE+0x3024)
#define SNGKS32C_ROMCON5       (ASIC_BASE+0x3028)
#define SNGKS32C_DRAMCON0      (ASIC_BASE+0x302c)
#define SNGKS32C_DRAMCON1      (ASIC_BASE+0x3030)
#define SNGKS32C_DRAMCON2      (ASIC_BASE+0x3034)
#define SNGKS32C_DRAMCON3      (ASIC_BASE+0x3038)
#define SNGKS32C_REFEXTCON     (ASIC_BASE+0x303c)

/* controller registers */
#define SNGKS32C_INTMODE       (ASIC_BASE+0x4000)
#define SNGKS32C_INTPEND       (ASIC_BASE+0x4004)
#define SNGKS32C_INTMASK       (ASIC_BASE+0x4008)
#define SNGKS32C_INTOFFSET     (ASIC_BASE+0x4024)
#define SNGKS32C_INTPENDTST    (ASIC_BASE+0x402c)

#define SNGKS32C_INTENB         SNGKS32C_INTMASK
#define SNGKS32C_INTDIS         SNGKS32C_INTMASK

#define SNGKS32C_INT_DISABLE        0x1fffff
#define SNGKS32C_INTNUMLEVELS       21
#define SNGKS32C_INTMASK_VAL        0x1fffff    
#define SNGKS32C_INTMODEIRQ         0x00

#define SNGKS32C_INTPRI0        (ASIC_BASE+0x400C)
#define SNGKS32C_INTPRI1        (ASIC_BASE+0x4010)
#define SNGKS32C_INTPRI2        (ASIC_BASE+0x4014)
#define SNGKS32C_INTPRI3        (ASIC_BASE+0x4018)
#define SNGKS32C_INTPRI4        (ASIC_BASE+0x401C)
#define SNGKS32C_INTPRI5        (ASIC_BASE+0x4020)

#define SNGKS32C_INTOSET_FIQ    (ASIC_BASE+0x4030)
#define SNGKS32C_INTOSET_IRQ    (ASIC_BASE+0x4034)

 /* I/O Port Interface  */

#define SNGKS32C_IOPMOD         (ASIC_BASE+0x5000)
#define SNGKS32C_IOPCON         (ASIC_BASE+0x5004)
#define SNGKS32C_IOPDATA        (ASIC_BASE+0x5008)

/* IIC Registers */
#define  SNGKS32C_IICCON        (ASIC_BASE+0xf000)
#define  SNGKS32C_IICBUF        (ASIC_BASE+0xf004)
#define  SNGKS32C_IICPS         (ASIC_BASE+0xf008)
#define  SNGKS32C_IICCNT        (ASIC_BASE+0xf00c)

/* definitions for the KS32C50100 UART */
#define SERIAL_A_BASE_ADR       (ASIC_BASE+0xD000)/* UART A base address */
#define SERIAL_B_BASE_ADR       (ASIC_BASE+0xE000)/* UART B base address */

#define SNGKS32C_TIMER_BASE      0x0A800000        /* Address of base of timer */



#endif






#ifdef __cplusplus
}
#endif

#endif /* __INCsngks32ch */