📄 cstartup_flash.s
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.section ".reset"
.text
#include "A_m40800.h"
# #include "arm.h"
# #include "maindef.h
.align
# ENTRY:
.globl _start
_start:
B InitReset
undefvec:
B undefvec
swivec:
# Software Interrupt
B swivec
pabtvec:
# Prefetch Abort
B pabtvec
dabtvec:
# Data Abort
B dabtvec
rsvdvec:
# reserved
B rsvdvec
irqvec:
# reserved
B irqvec
fiqvec:
# reserved
B fiqvec
VectorTable:
ldr pc, [pc, #0x18]
# SoftReset
ldr pc, [pc, #0x18]
# UndefHandler
ldr pc, [pc, #0x18]
# SWIHandler
ldr pc, [pc, #0x18]
# PrefetchAbortHandler
ldr pc, [pc, #0x18]
# DataAbortHandler
nop
# Reserved
ldr pc, [pc,#-0xF20]
# IRQ : read the AIC
ldr pc, [pc,#-0xF20]
# FIQ : read the AIC
# There are only 5 offsets as the vectoring is used.
.long SoftReset
.long UndefHandler
.long SWIHandler
.long PrefetchAbortHandler
.long DataAbortHandler
# Vectoring Execution function run at absolut addresss
SoftReset:
b SoftReset
UndefHandler:
b undef_program
SWIHandler:
b SWIHandler
PrefetchAbortHandler:
b undef_program
# b PrefetchAbortHandler
DataAbortHandler:
b undef_program
InitTableEBI:
.long EBI_CSR_0
.long EBI_CSR_1
.long EBI_CSR_2
.long EBI_CSR_3
.long EBI_CSR_4
.long EBI_CSR_5
.long EBI_CSR_6
.long EBI_CSR_7
.long 0x00000001
# REMAP command
.long 0x00000005
# 6 memory regions, standard read
PtEBIBase:
.long EBI_BASE
# EBI Base Address
InitReset:
ldr r0, PtEBIBase
ldr r1, [pc,#-(8+.-InitTableEBI)]
# values (relative)
# Speed up code execution by disabling wait state on Chip Select 0
str r1, [r0]
//guning bl __low_level_init
# Load the AIC Base Address and the default handler addresses
add r0, pc,#-(8+.-AicData)
ldmia r0, {r1-r4}
# Setup the Spurious Vector
str r4, [r1, #AIC_SPU]
# ICE note : For ICE debug
# Perform 8 End Of Interrupt Command to make sure AIC will not lock out nIRQ
# mov r0, #8
# LoopAic0:
# str r1, [r1, #AIC_EOICR]
# subs r0, r0, #1
# bhi LoopAic0
# Set up the default interrupt handler vectors
str r2, [r1, #AIC_SVR]
add r1, r1, #AIC_SVR
mov r0, #31
# counter
LoopAic1:
str r3, [r1, r0, LSL #2]
# SVRs for IRQs
subs r0, r0, #1
# do not save FIQ
bhi LoopAic1
b EndInitAic
# Default Interrupt Handlers
AicData:
.long AIC_BASE
# AIC Base Address
.global at91_default_fiq_handler
.global at91_default_irq_handler
.global at91_spurious_handler
PtDefaultHandler:
.long at91_default_fiq_handler
.long at91_default_irq_handler
.long at91_spurious_handler
EndInitAic:
# The RAM_BASE = 0 it's specific for ICE
mov r8,#RAM_BASE
# mov r8,#RAM_BASE_BOOT
# @ of the hard vector in internal RAM 0x300000
add r9, pc,#-(8+.-VectorTable)
ldmia r9!, {r0-r7}
# read 8 vectors
/* IF :DEF:SEMIHOSTING
# SWI it used to Ssemihosting features
stmia r8!, {r0-r1}
# store SoftReset ,UndefHandler
add r8, r8,#4
stmia r8!, {r3-r7}
# r2 = SWIHandler used for semihosting
ELSE */
# Without SEMIHOSTING
stmia r8!, {r0-r7}
# store them
// ENDIF
# End SEMIHOSTING
ldmia r9!, {r0-r4}
# read 5 absolute handler addresses
stmia r8!, {r0-r4}
# store them
# Copy the Image of the Memory Controller
sub r10, pc,#(8+.-InitTableEBI)
# get the address of the chip select register image
ldr r12, PtInitRemap
# get the real jump address ( after remap )
# Copy Chip Select Register Image to Memory Controller and command remap
ldmia r10!, {r0-r9,r11}
# load the complete image and the EBI base
# BL Init_Stack
# B __main
stmia r11!, {r0-r9}
# store the complete image with the remap command
# Jump to ROM at its new address
mov pc, r12
# jump and break the pipeline
PtInitRemap:
.long InitRemap
# address where to jump after REMAP
InitRemap:
#define IRQ_STACK_SIZE (3*8*4)
# 3 words per interrupt priority level
#define FIQ_STACK_SIZE (3*4)
# 3 words
#define ABT_STACK_SIZE (1*4)
# 1 word
#define UND_STACK_SIZE (1*4)
# 1 word
#define TOP_EXCEPTION_STACK 0x40000
# Defined in part
#define TOP_APPLICATION_STACK 0x3e000
# Defined in Target
ldr r0, =TOP_EXCEPTION_STACK
# Set up Fast Interrupt Mode and set FIQ Mode Stack
mov r5, #(ARM_MODE_FIQ | I_BIT | F_BIT)
msr CPSR_c, r5
mov r13, r0
# Init stack FIQ
sub r0, r0, #FIQ_STACK_SIZE
# Set up Interrupt Mode and set IRQ Mode Stack
mov r5, #(ARM_MODE_IRQ | I_BIT | F_BIT)
msr CPSR_c, r5
mov r13, r0
# Init stack IRQ
sub r0, r0, #IRQ_STACK_SIZE
# Set up Abort Mode and set Abort Mode Stack
mov r5, #(ARM_MODE_ABORT | I_BIT | F_BIT)
msr CPSR_c, r5
mov r13, r0
# Init stack Abort
sub r0, r0, #ABT_STACK_SIZE
# Set up Undefined Instruction Mode and set Undef Mode Stack
mov r5, #(ARM_MODE_UNDEF | I_BIT | F_BIT)
msr CPSR_c, r5
mov r13, r0
# Init stack Undef
sub r0, r0, #UND_STACK_SIZE
# Set up Supervisor Mode and set Supervisor Mode Stack
mov r5, #(ARM_MODE_SVC | I_BIT | F_BIT)
msr CPSR_c, r5
mov r13, r0
# Init stack Sup
mov r5, #ARM_MODE_USER
msr CPSR_c, r5
# set User mode
ldr r13, =TOP_APPLICATION_STACK
# Init stack User
.global Image_RO_Limit
# End of ROM code (=start of ROM data)
.global Image_RW_Base
# Base of RAM to initialise
.global Image_ZI_Base
# Base and limit of area
.global Image_ZI_Limit
# to zero initialise
ldr r0, =Image_RO_Limit
# Get pointer to ROM data
ldr r1, =Image_RW_Base
# and RAM copy
ldr r3, =Image_ZI_Base //guning
# Zero init base => top of initialised data
cmp r0, r1
# Check that they are different
beq NoRW
LoopRw : cmp r1, r3
# Copy init data
ldrcc r2, [r0], #4
strcc r2, [r1], #4
bcc LoopRw
NoRW: ldr r1, =Image_ZI_Limit //guning
# Top of zero init segment
mov r2, #0
LoopZI : cmp r3, r1
# Zero init
strcc r2, [r3], #4
bcc LoopZI
/* #if :DEF:SEMIHOSTING
.global __entry
SEMIHOSTING_STACK_SIZE EQU (8*1024)
ldr r0, = SEMIHOSTING_STACK_SIZE
sub r13, r13,r0
b __entry
else */
# not use SEMIHOSTING
.text
.global __main
// ldr r0, __main
mov lr, pc
// bx r0
bl __main
// #endif
.global c_undef_handler
undef_program:
# sub r14, r14, #4
# stmfd sp!, {r14}
# mrs r14, SPSR
# stmfd sp!, {r0, r14}
# mrs r14, CPSR
# bic r14, r14, #I_BIT
# orr r14, r14, #ARM_MODE_SYS
# msr CPSR, r14
# stmfd sp!, {r1-r3, r12, r14}
ldr r0, =c_undef_handler
mov r14, pc
bx r0
End:
b End
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