📄 or1200_du.v
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endcase//// Compare To What (Match Condition 2)//always @(dcr2 or id_pc or dcpu_adr_i or dcpu_dat_dc or dcpu_dat_lsu or dcpu_we_i) case (dcr2[`OR1200_DU_DCR_CT]) // synopsys parallel_case 3'b001: match_cond2_ct = id_pc; // insn fetch EA 3'b010: match_cond2_ct = dcpu_adr_i; // load EA 3'b011: match_cond2_ct = dcpu_adr_i; // store EA 3'b100: match_cond2_ct = dcpu_dat_dc; // load data 3'b101: match_cond2_ct = dcpu_dat_lsu; // store data 3'b110: match_cond2_ct = dcpu_adr_i; // load/store EA default:match_cond2_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; endcase//// When To Compare (Match Condition 2)//always @(dcr2 or dcpu_cycstb_i) case (dcr2[`OR1200_DU_DCR_CT]) // synopsys parallel_case 3'b000: match_cond2_stb = 1'b0; //comparison disabled 3'b001: match_cond2_stb = 1'b1; // insn fetch EA default:match_cond2_stb = dcpu_cycstb_i; // any load/store endcase//// Match Condition 2//always @(match_cond2_stb or dcr2 or dvr2 or match_cond2_ct) casex ({match_cond2_stb, dcr2[`OR1200_DU_DCR_CC]}) 4'b0_xxx, 4'b1_000, 4'b1_111: match2 = 1'b0; 4'b1_001: match2 = ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) == (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC])); 4'b1_010: match2 = ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) < (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC])); 4'b1_011: match2 = ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) <= (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC])); 4'b1_100: match2 = ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) > (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC])); 4'b1_101: match2 = ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) >= (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC])); 4'b1_110: match2 = ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) != (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC])); endcase//// Watchpoint 2//always @(dmr1 or match2 or wp) case (dmr1[`OR1200_DU_DMR1_CW2]) 2'b00: wp[2] = match2; 2'b01: wp[2] = match2 & wp[1]; 2'b10: wp[2] = match2 | wp[1]; 2'b11: wp[2] = 1'b0; endcase//// Compare To What (Match Condition 3)//always @(dcr3 or id_pc or dcpu_adr_i or dcpu_dat_dc or dcpu_dat_lsu or dcpu_we_i) case (dcr3[`OR1200_DU_DCR_CT]) // synopsys parallel_case 3'b001: match_cond3_ct = id_pc; // insn fetch EA 3'b010: match_cond3_ct = dcpu_adr_i; // load EA 3'b011: match_cond3_ct = dcpu_adr_i; // store EA 3'b100: match_cond3_ct = dcpu_dat_dc; // load data 3'b101: match_cond3_ct = dcpu_dat_lsu; // store data 3'b110: match_cond3_ct = dcpu_adr_i; // load/store EA default:match_cond3_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; endcase//// When To Compare (Match Condition 3)//always @(dcr3 or dcpu_cycstb_i) case (dcr3[`OR1200_DU_DCR_CT]) // synopsys parallel_case 3'b000: match_cond3_stb = 1'b0; //comparison disabled 3'b001: match_cond3_stb = 1'b1; // insn fetch EA default:match_cond3_stb = dcpu_cycstb_i; // any load/store endcase//// Match Condition 3//always @(match_cond3_stb or dcr3 or dvr3 or match_cond3_ct) casex ({match_cond3_stb, dcr3[`OR1200_DU_DCR_CC]}) 4'b0_xxx, 4'b1_000, 4'b1_111: match3 = 1'b0; 4'b1_001: match3 = ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) == (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC])); 4'b1_010: match3 = ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) < (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC])); 4'b1_011: match3 = ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) <= (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC])); 4'b1_100: match3 = ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) > (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC])); 4'b1_101: match3 = ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) >= (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC])); 4'b1_110: match3 = ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) != (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC])); endcase//// Watchpoint 3//always @(dmr1 or match3 or wp) case (dmr1[`OR1200_DU_DMR1_CW3]) 2'b00: wp[3] = match3; 2'b01: wp[3] = match3 & wp[2]; 2'b10: wp[3] = match3 | wp[2]; 2'b11: wp[3] = 1'b0; endcase//// Compare To What (Match Condition 4)//always @(dcr4 or id_pc or dcpu_adr_i or dcpu_dat_dc or dcpu_dat_lsu or dcpu_we_i) case (dcr4[`OR1200_DU_DCR_CT]) // synopsys parallel_case 3'b001: match_cond4_ct = id_pc; // insn fetch EA 3'b010: match_cond4_ct = dcpu_adr_i; // load EA 3'b011: match_cond4_ct = dcpu_adr_i; // store EA 3'b100: match_cond4_ct = dcpu_dat_dc; // load data 3'b101: match_cond4_ct = dcpu_dat_lsu; // store data 3'b110: match_cond4_ct = dcpu_adr_i; // load/store EA default:match_cond4_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; endcase//// When To Compare (Match Condition 4)//always @(dcr4 or dcpu_cycstb_i) case (dcr4[`OR1200_DU_DCR_CT]) // synopsys parallel_case 3'b000: match_cond4_stb = 1'b0; //comparison disabled 3'b001: match_cond4_stb = 1'b1; // insn fetch EA default:match_cond4_stb = dcpu_cycstb_i; // any load/store endcase//// Match Condition 4//always @(match_cond4_stb or dcr4 or dvr4 or match_cond4_ct) casex ({match_cond4_stb, dcr4[`OR1200_DU_DCR_CC]}) 4'b0_xxx, 4'b1_000, 4'b1_111: match4 = 1'b0; 4'b1_001: match4 = ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) == (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC])); 4'b1_010: match4 = ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) < (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC])); 4'b1_011: match4 = ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) <= (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC])); 4'b1_100: match4 = ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) > (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC])); 4'b1_101: match4 = ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) >= (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC])); 4'b1_110: match4 = ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) != (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC])); endcase//// Watchpoint 4//always @(dmr1 or match4 or wp) case (dmr1[`OR1200_DU_DMR1_CW4]) 2'b00: wp[4] = match4; 2'b01: wp[4] = match4 & wp[3]; 2'b10: wp[4] = match4 | wp[3]; 2'b11: wp[4] = 1'b0; endcase//// Compare To What (Match Condition 5)//always @(dcr5 or id_pc or dcpu_adr_i or dcpu_dat_dc or dcpu_dat_lsu or dcpu_we_i) case (dcr5[`OR1200_DU_DCR_CT]) // synopsys parallel_case 3'b001: match_cond5_ct = id_pc; // insn fetch EA 3'b010: match_cond5_ct = dcpu_adr_i; // load EA 3'b011: match_cond5_ct = dcpu_adr_i; // store EA 3'b100: match_cond5_ct = dcpu_dat_dc; // load data 3'b101: match_cond5_ct = dcpu_dat_lsu; // store data 3'b110: match_cond5_ct = dcpu_adr_i; // load/store EA default:match_cond5_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; endcase//// When To Compare (Match Condition 5)//always @(dcr5 or dcpu_cycstb_i) case (dcr5[`OR1200_DU_DCR_CT]) // synopsys parallel_case 3'b000: match_cond5_stb = 1'b0; //comparison disabled 3'b001: match_cond5_stb = 1'b1; // insn fetch EA default:match_cond5_stb = dcpu_cycstb_i; // any load/store endcase//// Match Condition 5//always @(match_cond5_stb or dcr5 or dvr5 or match_cond5_ct) casex ({match_cond5_stb, dcr5[`OR1200_DU_DCR_CC]}) 4'b0_xxx, 4'b1_000, 4'b1_111: match5 = 1'b0; 4'b1_001: match5 = ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) == (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC])); 4'b1_010: match5 = ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) < (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC])); 4'b1_011: match5 = ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) <= (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC])); 4'b1_100: match5 = ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) > (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC])); 4'b1_101: match5 = ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) >= (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC])); 4'b1_110: match5 = ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) != (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC])); endcase//// Watchpoint 5//always @(dmr1 or match5 or wp) case (dmr1[`OR1200_DU_DMR1_CW5]) 2'b00: wp[5] = match5; 2'b01: wp[5] = match5 & wp[4]; 2'b10: wp[5] = match5 | wp[4]; 2'b11: wp[5] = 1'b0; endcase//// Compare To What (Match Condition 6)//always @(dcr6 or id_pc or dcpu_adr_i or dcpu_dat_dc or dcpu_dat_lsu or dcpu_we_i) case (dcr6[`OR1200_DU_DCR_CT]) // synopsys parallel_case 3'b001: match_cond6_ct = id_pc; // insn fetch EA 3'b010: match_cond6_ct = dcpu_adr_i; // load EA 3'b011: match_cond6_ct = dcpu_adr_i; // store EA 3'b100: match_cond6_ct = dcpu_dat_dc; // load data 3'b101: match_cond6_ct = dcpu_dat_lsu; // store data 3'b110: match_cond6_ct = dcpu_adr_i; // load/store EA default:match_cond6_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; endcase//// When To Compare (Match Condition 6)//always @(dcr6 or dcpu_cycstb_i) case (dcr6[`OR1200_DU_DCR_CT]) // synopsys parallel_case 3'b000: match_cond6_stb = 1'b0; //comparison disabled 3'b001: match_cond6_stb = 1'b1; // insn fetch EA default:match_cond6_stb = dcpu_cycstb_i; // any load/store endcase//// Match Condition 6//always @(match_cond6_stb or dcr6 or dvr6 or match_cond6_ct) casex ({match_cond6_stb, dcr6[`OR1200_DU_DCR_CC]}) 4'b0_xxx, 4'b1_000, 4'b1_111: match6 = 1'b0; 4'b1_001: match6 = ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) == (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC])); 4'b1_010: match6 = ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) < (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC])); 4'b1_011: match6 = ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) <= (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC])); 4'b1_100: match6 = ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) > (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC])); 4'b1_101: match6 = ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) >= (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC])); 4'b1_110: match6 = ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) != (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC])); endcase//// Watchpoint 6//always @(dmr1 or match6 or wp) case (dmr1[`OR1200_DU_DMR1_CW6]) 2'b00: wp[6] = match6; 2'b01: wp[6] = match6 & wp[5]; 2'b10: wp[6] = match6 | wp[5]; 2'b11: wp[6] = 1'b0; endcase//// Compare To What (Match Condition 7)//always @(dcr7 or id_pc or dcpu_adr_i or dcpu_dat_dc or dcpu_dat_lsu or dcpu_we_i) case (dcr7[`OR1200_DU_DCR_CT]) // synopsys parallel_case 3'b001: match_cond7_ct = id_pc; // insn fetch EA 3'b010: match_cond7_ct = dcpu_adr_i; // load EA 3'b011: match_cond7_ct = dcpu_adr_i; // store EA 3'b100: match_cond7_ct = dcpu_dat_dc; // load data 3'b101: match_cond7_ct = dcpu_dat_lsu; // store data 3'b110: match_cond7_ct = dcpu_adr_i; // load/store EA default:match_cond7_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; endcase//// When To Compare (Match Condition 7)//always @(dcr7 or dcpu_cycstb_i) case (dcr7[`OR1200_DU_DCR_CT]) // synopsys parallel_case 3'b000: match_cond7_stb = 1'b0; //comparison disabled 3'b001: match_cond7_stb = 1'b1; // insn fetch EA default:match_cond7_stb = dcpu_cycstb_i; // any load/store endcase//// Match Condition 7//always @(match_cond7_stb or dcr7 or dvr7 or match_cond7_ct) casex ({match_cond7_stb, dcr7[`OR1200_DU_DCR_CC]}) 4'b0_xxx, 4'b1_000, 4'b1_111: match7 = 1'b0; 4'b1_001: match7 = ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) == (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC])); 4'b1_010: match7 = ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) < (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC])); 4'b1_011: match7 = ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) <= (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC])); 4'b1_100: match7 = ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) > (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC])); 4'b1_101: match7 = ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) >= (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC])); 4'b1_110: match7 = ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) != (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC])); endcase//// Watchpoint 7//always @(dmr1 or match7 or wp) case (dmr1[`OR1200_DU_DMR1_CW7]) 2'b00: wp[7] = match7; 2'b01: wp[7] = match7 & wp[6]; 2'b10: wp[7] = match7 | wp[6]; 2'b11: wp[7] = 1'b0; endcase//// Increment Watchpoint Counter 0//always @(wp or dmr2) if (dmr2[`OR1200_DU_DMR2_WCE0]) incr_wpcntr0 = |(wp & ~dmr2[`OR1200_DU_DMR2_AWTC]); else incr_wpcntr0 = 1'b0;//// Match Condition Watchpoint Counter 0//always @(dwcr0) if (dwcr0[`OR1200_DU_DWCR_MATCH] == dwcr0[`OR1200_DU_DWCR_COUNT]) wpcntr0_match = 1'b1; else wpcntr0_match = 1'b0;//// Watchpoint 8//always @(dmr1 or wpcntr0_match or wp) case (dmr1[`OR1200_DU_DMR1_CW8]) 2'b00: wp[8] = wpcntr0_match; 2'b01: wp[8] = wpcntr0_match & wp[7]; 2'b10: wp[8] = wpcntr0_match | wp[7]; 2'b11: wp[8] = 1'b0; endcase//// Increment Watchpoint Counter 1//always @(wp or dmr2) if (dmr2[`OR1200_DU_DMR2_WCE1]) incr_wpcntr1 = |(wp & dmr2[`OR1200_DU_DMR2_AWTC]); else incr_wpcntr1 = 1'b0;//// Match Condition Watchpoint Counter 1//always @(dwcr1) if (dwcr1[`OR1200_DU_DWCR_MATCH] == dwcr1[`OR1200_DU_DWCR_COUNT]) wpcntr1_match = 1'b1; else wpcntr1_match = 1'b0;//// Watchpoint 9//always @(dmr1 or wpcntr1_match or wp) case (dmr1[`OR1200_DU_DMR1_CW9]) 2'b00: wp[9] = wpcntr1_match; 2'b01: wp[9] = wpcntr1_match & wp[8]; 2'b10: wp[9] = wpcntr1_match | wp[8]; 2'b11: wp[9] = 1'b0; endcase//// Watchpoint 10//always @(dmr1 or dbg_ewt_i or wp) case (dmr1[`OR1200_DU_DMR1_CW10]) 2'b00: wp[10] = dbg_ewt_i; 2'b01: wp[10] = dbg_ewt_i & wp[9]; 2'b10: wp[10] = dbg_ewt_i | wp[9]; 2'b11: wp[10] = 1'b0; endcase`endif//// Watchpoints can cause trap exception//`ifdef OR1200_DU_HWBKPTSassign du_hwbkpt = |(wp & dmr2[`OR1200_DU_DMR2_WGB]);`elseassign du_hwbkpt = 1'b0;`endif`ifdef OR1200_DU_TB_IMPLEMENTED//// Simple trace buffer// (right now hardcoded for Xilinx Virtex FPGAs)//// Stores last 256 instruction addresses, instruction// machine words and ALU results////// Trace buffer write enable//assign tb_enw = ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]);//// Trace buffer write address pointer//always @(posedge clk or posedge rst) if (rst) tb_wadr <= #1 8'h00; else if (tb_enw) tb_wadr <= #1 tb_wadr + 8'd1;//// Free running counter (time stamp)//always @(posedge clk or posedge rst) if (rst) tb_timstmp <= #1 32'h00000000; else if (!dbg_bp_r) tb_timstmp <= #1 tb_timstmp + 32'd1;//// Trace buffer RAMs//or1200_dpram_256x32 tbia_ram( .clk_a(clk), .rst_a(rst), .addr_a(spr_addr[7:0]), .ce_a(1'b1), .oe_a(1'b1), .do_a(tbia_dat_o), .clk_b(clk), .rst_b(rst), .addr_b(tb_wadr), .di_b(spr_dat_npc), .ce_b(1'b1), .we_b(tb_enw));or1200_dpram_256x32 tbim_ram( .clk_a(clk), .rst_a(rst), .addr_a(spr_addr[7:0]), .ce_a(1'b1), .oe_a(1'b1), .do_a(tbim_dat_o), .clk_b(clk), .rst_b(rst), .addr_b(tb_wadr), .di_b(ex_insn), .ce_b(1'b1), .we_b(tb_enw));or1200_dpram_256x32 tbar_ram( .clk_a(clk), .rst_a(rst), .addr_a(spr_addr[7:0]), .ce_a(1'b1), .oe_a(1'b1), .do_a(tbar_dat_o), .clk_b(clk), .rst_b(rst), .addr_b(tb_wadr), .di_b(rf_dataw), .ce_b(1'b1), .we_b(tb_enw));or1200_dpram_256x32 tbts_ram( .clk_a(clk), .rst_a(rst), .addr_a(spr_addr[7:0]), .ce_a(1'b1), .oe_a(1'b1), .do_a(tbts_dat_o), .clk_b(clk), .rst_b(rst), .addr_b(tb_wadr), .di_b(tb_timstmp), .ce_b(1'b1), .we_b(tb_enw));`elseassign tbia_dat_o = 32'h0000_0000;assign tbim_dat_o = 32'h0000_0000;assign tbar_dat_o = 32'h0000_0000;assign tbts_dat_o = 32'h0000_0000;`endif // OR1200_DU_TB_IMPLEMENTED`else // OR1200_DU_IMPLEMENTED//// When DU is not implemented, drive all outputs as would when DU is disabled//assign dbg_bp_o = 1'b0;assign du_dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};assign du_hwbkpt = 1'b0;//// Read DU registers//`ifdef OR1200_DU_READREGSassign spr_dat_o = 32'h0000_0000;`ifdef OR1200_DU_UNUSED_ZERO`endif`endif`endifendmodule⌨️ 快捷键说明
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