coregen.log

蜂鸣器控制

# Xilinx CORE Generator 6.3.03i
# User = mail007
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in E:\RHicdemo\demo\pro012\ise63_pro\coregen.log
# busformat=BusFormatAngleBracketNotRipped
# designflow=VHDL
# expandedprojectpath=E:\RHicdemo\demo\pro012\ise63_pro
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=VHDL
# xilinxfamily=Virtex2
# outputoption=DesignFlow
# overwritefiles=Default
# simvendor=ModelSim
# expandedprojectpath=E:\RHicdemo\demo\pro012\ise63_pro
SETPROJECT .
Set current Project to E:\RHicdemo\demo\pro012\ise63_pro
SET BusFormat = BusFormatAngleBracketNotRipped
SETXIPCPORTHOST 1033
XIPCPJSENDCORES spartan3