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=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 3s50pq208-4 Number of Slices: 115 out of 768 14% Number of Slice Flip Flops: 91 out of 1536 5% Number of 4 input LUTs: 215 out of 1536 13% Number of bonded IOBs: 17 out of 124 13% Number of GCLKs: 1 out of 8 12% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk | BUFGP | 44 |clk_cnt_23:Q | NONE | 31 |clk_cnt_2:Q | NONE | 14 |song_inst_carry(song_inst_carry29:O)| NONE(*)(song_inst_sp_1)| 2 |-----------------------------------+------------------------+-------+(*) This 1 clock signal(s) are generated by combinatorial logic,and XST is not able to identify which are the primary clock signals.Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.Timing Summary:---------------Speed Grade: -4 Minimum period: 7.683ns (Maximum Frequency: 130.157MHz) Minimum input arrival time before clock: No path found Maximum output required time after clock: 9.328ns Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".
Started process "Translate".Command Line: ngdbuild -intstyle ise -dd e:\rhicdemo\demo\pro012\ise63_pro/_ngo-uc ../rtl/song_top.ucf -p xc3s50-pq208-4 song_top.ngc song_top.ngd Reading NGO file "e:/rhicdemo/demo/pro012/ise63_pro/song_top.ngc" ...Reading component libraries for design expansion...Loading design module "e:\rhicdemo\demo\pro012\ise63_pro/led_top.ngc"...Annotating constraints to design from file "../rtl/song_top.ucf" ...Checking timing specifications ...Checking expanded design ...WARNING:NgdBuild:478 - clock net 'rst_n_IBUFG' drives no clock pinsNGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 1Total memory usage is 40296 kilobytesWriting NGD file "song_top.ngd" ...Writing NGDBUILD log file "song_top.bld"...NGDBUILD done.Completed process "Translate".
Started process "Map".Using target part "3s50pq208-4".Removing unused or disabled logic...Running cover...Running directed packing...Running delay-based LUT packing...Running related packing...Design Summary:Number of errors: 0Number of warnings: 1Logic Utilization: Number of Slice Flip Flops: 90 out of 1,536 5% Number of 4 input LUTs: 160 out of 1,536 10%Logic Distribution: Number of occupied Slices: 113 out of 768 14% Number of Slices containing only related logic: 113 out of 113 100% Number of Slices containing unrelated logic: 0 out of 113 0% *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs: 209 out of 1,536 13% Number used as logic: 160 Number used as a route-thru: 49 Number of bonded IOBs: 18 out of 124 14% IOB Flip Flops: 1 Number of GCLKs: 1 out of 8 12%Total equivalent gate count for design: 2,087Additional JTAG gate count for IOBs: 864Peak Memory Usage: 66 MBNOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design.Mapping completed.See MAP report file "song_top_map.mrp" for details.Completed process "Map".Mapping Module song_top . . .
MAP command line:
map -intstyle ise -p xc3s50-pq208-4 -cm area -pr b -k 4 -c 100 -tx off -o song_top_map.ncd song_top.ngd song_top.pcf
Mapping Module song_top: DONE
Started process "Place & Route".Constraints file: song_top.pcfLoading device database for application Par from file "song_top_map.ncd". "song_top" is an NCD, version 2.38, device xc3s50, package pq208, speed -4Loading device for application Par from file '3s50.nph' in environmentD:/Xilinx.Device speed data version: PRODUCTION 1.35 2004-11-11.Resolving physical constraints.Finished resolving physical constraints.Device utilization summary: Number of External IOBs 18 out of 124 14% Number of LOCed External IOBs 15 out of 18 83% Number of Slices 113 out of 768 14% Number of BUFGMUXs 1 out of 8 12%Overall effort level (-ol): Standard (set by user)Placer effort level (-pl): Standard (set by user)Placer cost table entry (-t): 1Router effort level (-rl): Standard (set by user)Phase 1.1Phase 1.1 (Checksum:989949) REAL time: 2 secs .Phase 3.3Phase 3.3 (Checksum:1c9c37d) REAL time: 2 secs Phase 4.5Phase 4.5 (Checksum:26259fc) REAL time: 2 secs Phase 5.8................................Phase 5.8 (Checksum:99bc58) REAL time: 2 secs Phase 6.5Phase 6.5 (Checksum:39386fa) REAL time: 2 secs Phase 7.18Phase 7.18 (Checksum:42c1d79) REAL time: 2 secs Writing design to file song_top.ncd.Total REAL time to Placer completion: 3 secs Total CPU time to Placer completion: 2 secs Phase 1: 747 unrouted; REAL time: 3 secs Phase 2: 716 unrouted; REAL time: 3 secs Phase 3: 297 unrouted; REAL time: 3 secs Phase 4: 0 unrouted; REAL time: 3 secs Total REAL time to Router completion: 3 secs Total CPU time to Router completion: 2 secs Generating "par" statistics.**************************Generating Clock Report**************************+-------------------------+----------+------+------+------------+-------------+| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|+-------------------------+----------+------+------+------------+-------------+| clk_BUFGP | BUFGMUX0| No | 22 | 0.099 | 0.711 |+-------------------------+----------+------+------+------------+-------------+| clk_cnt<2> | Local | | 9 | 0.338 | 1.118 |+-------------------------+----------+------+------+------------+-------------+| song_inst_carry | Local | | 16 | 0.218 | 1.621 |+-------------------------+----------+------+------+------------+-------------+| clk_cnt<23> | Local | | 28 | 2.742 | 3.552 |+-------------------------+----------+------+------+------------+-------------+Generating Pad Report.All signals are completely routed.Total REAL time to PAR completion: 4 secs Total CPU time to PAR completion: 3 secs Peak Memory Usage: 53 MBPlacement: Completed - No errors found.Routing: Completed - No errors found.Writing design to file song_top.ncd.PAR done.Completed process "Place & Route".Started process "Generate Post-Place & Route Static Timing".Analysis completed Sat Dec 03 13:42:29 2005--------------------------------------------------------------------------------Generating Report ...Completed process "Generate Post-Place & Route Static Timing".Place & Route Module song_top . . .
PAR command line: par -w -intstyle ise -ol std -t 1 song_top_map.ncd song_top.ncd song_top.pcf
PAR completed successfully
Started process "Generate Programming File".WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net song_inst_carry is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.Completed process "Generate Programming File".
Project Navigator Auto-Make Log File-------------------------------------
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Project Navigator Auto-Make Log File-------------------------------------
deleting __projnav/ise63_pro.gfldeleting __projnav/ise63_pro_flowplus.gflFinished cleaning up project
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