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-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "../rtl/buzzer.v"
Module <buzzer> compiled
No errors in compilation
Analysis of file <buzzer.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <buzzer>.
WARNING:Xst:883 - ../rtl/buzzer.v line 27: Ignored duplicate item in case statement. 
Module <buzzer> is correct for synthesis.
 
    Set property "buffer_type = ibufg" for signal <rst_n> in unit <buzzer>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <buzzer>.
    Related source file is ../rtl/buzzer.v.
    Found 1-bit 4-to-1 multiplexer for signal <sp>.
    Found 28-bit up counter for signal <cnt>.
    Found 2-bit up counter for signal <led_cnt>.
    Summary:
	inferred   2 Counter(s).
	inferred   1 Multiplexer(s).
Unit <buzzer> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 2
 28-bit up counter                 : 1
 2-bit up counter                  : 1
# Multiplexers                     : 1
 1-bit 4-to-1 multiplexer          : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <cnt_27> is unconnected in block <buzzer>.
WARNING:Xst:1291 - FF/Latch <cnt_25> is unconnected in block <buzzer>.
WARNING:Xst:1291 - FF/Latch <cnt_26> is unconnected in block <buzzer>.

Optimizing unit <buzzer> ...
Loading device for application Xst from file '3s50.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block buzzer, actual ratio is 2.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s50pq208-4 

 Number of Slices:                      16  out of    768     2%  
 Number of Slice Flip Flops:            27  out of   1536     1%  
 Number of 4 input LUTs:                31  out of   1536     2%  
 Number of bonded IOBs:                  5  out of    124     4%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
cnt_24:Q                           | NONE                   | 2     |
clk                                | BUFGP                  | 25    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 4.590ns (Maximum Frequency: 217.865MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 7.323ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd e:\rhicdemo\demo\pro012\ise63_pro/_ngo
-uc ../rtl/buzzer.ucf -p xc3s50-pq208-4 buzzer.ngc buzzer.ngd 

Reading NGO file "e:/rhicdemo/demo/pro012/ise63_pro/buzzer.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "../rtl/buzzer.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:478 - clock net 'rst_n_IBUFG' drives no clock pins

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   1

Total memory usage is 39272 kilobytes

Writing NGD file "buzzer.ngd" ...

Writing NGDBUILD log file "buzzer.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "3s50pq208-4".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:          27 out of   1,536    1%
  Number of 4 input LUTs:               6 out of   1,536    1%
Logic Distribution:
  Number of occupied Slices:                           16 out of     768    2%
    Number of Slices containing only related logic:      16 out of      16  100%
    Number of Slices containing unrelated logic:          0 out of      16    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:             30 out of   1,536    1%
  Number used as logic:                  6
  Number used as a route-thru:          24
  Number of bonded IOBs:                6 out of     124    4%
  Number of GCLKs:                     1 out of       8   12%

Total equivalent gate count for design:  402
Additional JTAG gate count for IOBs:  288
Peak Memory Usage:  64 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "buzzer_map.mrp" for details.
Completed process "Map".

Mapping Module buzzer . . .
MAP command line:
map -intstyle ise -p xc3s50-pq208-4 -cm area -pr b -k 4 -c 100 -tx off -o buzzer_map.ncd buzzer.ngd buzzer.pcf
Mapping Module buzzer: DONE



Started process "Place & Route".





Constraints file: buzzer.pcf

Loading device database for application Par from file "buzzer_map.ncd".
   "buzzer" is an NCD, version 2.38, device xc3s50, package pq208, speed -4
Loading device for application Par from file '3s50.nph' in environment
D:/Xilinx.
Device speed data version:  PRODUCTION 1.35 2004-11-11.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External IOBs             6 out of 124     4%
      Number of LOCed External IOBs    3 out of 6      50%

   Number of Slices                   16 out of 768     2%

   Number of BUFGMUXs                  1 out of 8      12%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9896ab) REAL time: 2 secs 

.
Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.8
.
Phase 5.8 (Checksum:98b911) REAL time: 2 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 2 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 2 secs 

Writing design to file buzzer.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 84 unrouted;       REAL time: 3 secs 

Phase 2: 70 unrouted;       REAL time: 3 secs 

Phase 3: 2 unrouted;       REAL time: 3 secs 

Phase 4: 0 unrouted;       REAL time: 3 secs 

Total REAL time to Router completion: 3 secs 
Total CPU time to Router completion: 1 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|         clk_BUFGP       |  BUFGMUX0| No   |   13 |  0.097     |  0.716      |
+-------------------------+----------+------+------+------------+-------------+
|           cnt<24>       |   Local  |      |    3 |  0.000     |  1.424      |
+-------------------------+----------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 4 secs 
Total CPU time to PAR completion: 2 secs 

Peak Memory Usage:  52 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file buzzer.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".


Analysis completed Sat Dec 03 13:39:24 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module buzzer . . .
PAR command line: par -w -intstyle ise -ol std -t 1 buzzer_map.ncd buzzer.ncd buzzer.pcf
PAR completed successfully




Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "../rtl/song.v"
Module <song> compiled
Compiling source file "../netlist/xst/led_top_inst.v"
Module <led_top> compiled
Compiling source file "../rtl/song_top.v"
Module <song_top> compiled
No errors in compilation
Analysis of file <song_top.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <song_top>.
Module <song_top> is correct for synthesis.
 
    Set property "buffer_type = ibufg" for signal <rst_n> in unit <song_top>.
Analyzing module <song>.
Module <song> is correct for synthesis.
 
Analyzing module <led_top>.
Generating a Black Box for module <led_top>.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <song>.
    Related source file is ../rtl/song.v.
    Found 4-bit register for signal <med>.
    Found 4-bit register for signal <high>.
    Found 4-bit register for signal <low>.
    Found 1-bit register for signal <sp>.
    Found 8-bit adder for signal <$n0010> created at line 53.
    Found 8-bit register for signal <counter>.
    Found 14-bit up counter for signal <divider>.
    Found 14-bit register for signal <origin>.
    Summary:
	inferred   1 Counter(s).
	inferred  35 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <song> synthesized.


Synthesizing Unit <song_top>.
    Related source file is ../rtl/song_top.v.
WARNING:Xst:1780 - Signal <segcode> is never used or assigned.
WARNING:Xst:1780 - Signal <led_w> is never used or assigned.
WARNING:Xst:1780 - Signal <hex> is never used or assigned.
    Found 24-bit up counter for signal <clk_cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <song_top> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 8-bit adder                       : 1
# Counters                         : 2
 14-bit up counter                 : 1
 24-bit up counter                 : 1
# Registers                        : 6
 1-bit register                    : 1
 14-bit register                   : 1
 8-bit register                    : 1
 4-bit register                    : 3

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Reading core <led_top.ngc>.
Loading core <led_top> for timing and area information for instance <led_top_inst>.
WARNING:Xst:1710 - FF/Latch  <med_3> (without init value) is constant in block <song>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <high_3> (without init value) is constant in block <song>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <low_3> (without init value) is constant in block <song>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <high_1> (without init value) is constant in block <song>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <high_2> (without init value) is constant in block <song>.

Optimizing unit <song_top> ...

Optimizing unit <song> ...
Loading device for application Xst from file '3s50.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block song_top, actual ratio is 15.
FlipFlop song_inst_med_0 has been replicated 1 time(s)
FlipFlop song_inst_med_1 has been replicated 1 time(s)
FlipFlop song_inst_sp has been replicated 1 time(s) to handle iob=true attribute.