ise63_pro.npl

蜂鸣器控制

JDF G
// Created by Project Navigator ver 1.0
PROJECT ise63_pro
DESIGN ise63_pro
DEVFAM spartan3
DEVFAMTIME 0
DEVICE xc3s50
DEVICETIME 0
DEVPKG pq208
DEVPKGTIME 0
DEVSPEED -4
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL Verilog
GENERATEDSIMULATIONMODELTIME 0
SOURCE ..\rtl\buzzer.v
SOURCE ..\rtl\song_top.v
SOURCE ..\rtl\song.v
SOURCE ..\netlist\xst\led_top_inst.v
DEPASSOC buzzer ..\rtl\buzzer.ucf
DEPASSOC song_top ..\rtl\song_top.ucf
[Normal]
xilxBitgStart_Clk=xstvlg, spartan3, Verilog.t_bitFile, 1133588319, JTAG Clock
[STRATEGY-LIST]
Normal=True