song_top.v

来自「蜂鸣器控制」· Verilog 代码 · 共 77 行

////////////////////////////////////////////////////////////////////////////////
//       ____  _      __  ___                                                 //
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//  consent of RicHic Inc.                                                    //
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//    (c) 2003, 2004, 2005 RicHic Inc.                                        //
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////////////////////////////////////////////////////////////////////////////////

//  本设计在RicHic开发系统中验证通过
//


module song_top
    (
	sp,    
	seg,
	led,
  	clk,
	rst_n
    );
output	        sp;
output   [11:0] seg;
output  [2:0]   led;
input	        clk;
input	        rst_n; // synthesis attribute clock_buffer of rst_n is ibufg;

reg     [23:0]   clk_cnt;
  always @ ( posedge clk or negedge rst_n)
    if (!rst_n )
        clk_cnt <= 24'd0;
    else
        clk_cnt <= clk_cnt + 1'b1;

  wire  clk_6mhz = clk_cnt[2];
  wire  clk_4hz  = clk_cnt[23];
      
wire    [3:0]   high,med,low;      
wire    [6 :0]      led_w ;
wire    [4 :0]      segcode;
wire    [3 :0]      hex;

  assign    led[0] = |{high,med,low};
  assign    led[1] = |{high,med};
  assign    led[2] = |high;
song song_inst
    (
    .clk_6mhz   (clk_6mhz), 
    .clk_4hz    (clk_4hz),
    .sp         ( sp    ),
    .high       ( high  ),
    .med        ( med   ),
    .low        ( low   )
    );

led_top led_top_inst(
    .seg    ( seg   ),    
    .clk    ( clk   ),
    .rst_n  ( rst_n ), 
    .data   ( {4'h0,high,med,low}),
    .dot    ( 4'b0000)
    );


endmodule