xunwen.lst

TI microprocessor, most about CAN2.0 development

TMS320C1x/C2x/C2xx/C5x COFF Assembler       Version 6.60     Fri Aug 31 10:29:26 2007
Copyright (c) 1987-1995  Texas Instruments Incorporated 

Work\xunwen.asm                                                      PAGE    1

       1                    .include 24x.h    
       2                    .include xunwen.h
       3                    .include initcan.asm
       4                       
       5            ;;;;;;;;;.bss .usect .text .data .sect .asect total  six kinds of sections
       6 0000               .bss GPR0,1  
       7 0001               .bss GPR1,1   
       8 0002               .bss GPR2,1
       9 0003               .bss CanId,1 
      10 0004               .bss SendFlag,1
      11             
      12 0000       var   .usect "newvars",7
      13 0007       inbuf .usect "newvars",7
      14             
      15 0000               .data
      16 0000 0011  coeff: .word 0011h,0022h,0033h
         0001 0022  
         0002 0033  
      17             
      18 0000               .text  
      19 0000       START:  
      20 0000 bc00          LDP     #0
      21 0001 be41      SETC        INTM            ;Disable all interrupts
      22 0002 ae04          SPLK    #0000H, IMR         ;Mask all core ints
         0003 0000  
      23 0004 1006          LACC    IFR                             ;Read Interrupt flags
      24 0005 9006          SACL    IFR                             ;Clear all ints flags
      25 0006 be46          CLRC    SXM             ;Clear Sign Extension Mode
      26 0007 be42          CLRC    OVM             ;Reset Overflow Mode
      27 0008 be45          SETC    CNF             ;Config Block B0 to Data mem.
      28            
      29 0009 bce0          LDP     #00E0h
      30 000a ae29          SPLK    #002Fh, WDCR            ;Enable Interal Watchdog
         000b 002f  
      31 000c               KICK_DOG    
1        000c bce0          LDP     #00E0h
1        000d ae25          SPLK    #05555h, WDKEY
         000e 5555  
1        000f ae25          SPLK    #0AAAAh, WDKEY
         0010 aaaa  
1        0011 bc00          LDP     #0h
      32                    
      33 0012 bc00          LDP     #0
      34 0013 ae00-         SPLK    #0h, GPR0               ;Set wait state generator for:
         0014 0000  
      35 0015 0c00-         OUT     GPR0, WSGR              ;Program Space, 0-7 wait states
         0016 ffff  
      36 0017 bce0          LDP     #00E0h
      37 0018 ae18          SPLK    #0000h,SCSR     ;CLKOUT=CPUCLK
         0019 0000  
      38            
      39 001a bce1          LDP     #OCRA>>7                ;Get the OCRA Register offset address
      40 001b ae10          SPLK    #0000h,  OCRA           ;IOPA,IOPB as I/O port 
         001c 0000  
      41 001d ae12          SPLK    #02C3h,  OCRB           ;IOPC6-7,CANTX,CANRX ,IOPD1 as Interrupt
TMS320C1x/C2x/C2xx/C5x COFF Assembler       Version 6.60     Fri Aug 31 10:29:26 2007
Copyright (c) 1987-1995  Texas Instruments Incorporated 

Work\xunwen.asm                                                      PAGE    2

         001e 02c3  
      42 001f ae18          SPLK    #0FF00h, PADATDIR       ;PORT A ,all as output low 
         0020 ff00  
      43 0021 ae1a          SPLK    #0FF00h, PBDATDIR       ;PORT B ,all as output low      
         0022 ff00  
      44 0023 ae1c          SPLK    #3F30h,  PCDATDIR       ;PORT C, all as output low except CAN
         0024 3f30  
      45 0025 ae1e          SPLK    #0100h,  PDDATDIR   ;PORT D, IOPD-0,output,IOPD-1 input
         0026 0100  
      46            
      47 0027 bce8          LDP             #EVIMRC>>7              
      48 0028 ae2e          SPLK    #0, EVIMRC              ;CAP0-2 Disable 
         0029 0000  
      49 002a ae2d          SPLK    #1, EVIMRB              ;GP Timer 2 period interrupt enabled
         002b 0001  
      50 002c ae08          SPLK    #0101011101000100b, T2CON; clk = 16Mhz/128 (125k)
         002d 5744  
      51                                                    ;010 Stop after current timer period is complete on emulation suspend
      52                                                    ;10 Continuous up-count mode
      53                                                    ;111 x/128
      54                                                    ;0 Use own TENABLE BIT
      55                                                    ;1 Enable timer operations
      56                                                    ;00 Internal clk
      57                                                    ;01 LD CMPR When counter value is 0 or equals period register value
      58                                                    ;0 Disable timer compare operation
      59                                                    ;0 use own period register
      60 002e ae00          SPLK    #0000h,  GPTCON
         002f 0000  
      61 0030 ae07          SPLK    #0ffffh, T2PR           ; period = 65536 (0.5s approx)
         0031 ffff  
      62            
      63 0032 bce0          LDP     #XINT1CR>>7
      64 0033 ae70          SPLK    #0005h, XINT1CR ;rising edge int, High prority, Enable Xint1 interrupt
         0034 0005  
      65 0035 ae71          SPLK    #0005h, XINT2CR ;rising edge int, High prority, Enable Xint2 interrupt
         0036 0005  
      66            
      67 0037 bc00          LDP #0
      68 0038 ae04          SPLK #0005H,IMR         ;Enable Can,Xint1,xint2(int1) & timer 2 interrupt (int3)        
         0039 0005  
      69                    
      70 003a 7a80          call    SetCan 
         003b 0040+ 
      71                    
      72 003c be40          CLRC    INTM
      73 003d               OnLed
1        003d bce1          LDP     #PADATDIR>>7
1        003e 6918      LACL        PADATDIR
1        003f bfb0          AND     #0FFFBH
         0040 fffb  
1        0041 9018          SACL    PADATDIR
1        0042 bc00          LDP     #0
      74                            
      75 0043       LOOP:   
      76 0043               ClrWDI
TMS320C1x/C2x/C2xx/C5x COFF Assembler       Version 6.60     Fri Aug 31 10:29:26 2007
Copyright (c) 1987-1995  Texas Instruments Incorporated 

Work\xunwen.asm                                                      PAGE    3

1        0043 bce1          LDP     #PADATDIR>>7
1        0044 6918      LACL        PADATDIR
1        0045 bfb0          AND     #0FF7FH
         0046 ff7f  
1        0047 9018          SACL    PADATDIR
1        0048 bc00          LDP     #0
      77 0049 8b00          NOP 
      78 004a 8b00          NOP 
      79 004b be22          IDLE
      80 004c 8b00          NOP 
      81 004d 8b00          NOP
      82 004e               SetWDI
1        004e bce1          LDP     #PADATDIR>>7
1        004f 6918      LACL        PADATDIR
1        0050 bfc0          OR      #0080H
         0051 0080  
1        0052 9018          SACL    PADATDIR
1        0053 bc00          LDP     #0
      83 0054 8b00          NOP
      84 0055 8b00          NOP
      85 0056 7980          B LOOP  
         0057 0043' 
      86                     
      87 0058       PHANTOM:
      88 0058               KICK_DOG                        ;Resets WD counter
1        0058 bce0          LDP     #00E0h
1        0059 ae25          SPLK    #05555h, WDKEY
         005a 5555  
1        005b ae25          SPLK    #0AAAAh, WDKEY
         005c aaaa  
1        005d bc00          LDP     #0h
      89 005e 7980      B PHANTOM 
         005f 0058' 
      90            ;/////////////////////////////////////////////
      91 0060       GISR1:
      92 0060 8b00          NOP
      93 0061 ef00          RET
      94 0062       GISR3:
      95 0062 8b00          NOP
      96 0063 ef00          RET      
      97             
      98             

 No Errors,  No Warnings