xunwen.asm

TI microprocessor, most about CAN2.0 development

	.include 24x.h    
	.include xunwen.h
	.include initcan.asm
           
;;;;;;;;;.bss .usect .text .data .sect .asect total  six kinds of sections
 	.bss GPR0,1  
 	.bss GPR1,1   
 	.bss GPR2,1
 	.bss CanId,1 
 	.bss SendFlag,1
 
var   .usect "newvars",7
inbuf .usect "newvars",7
 
 	.data
coeff: .word 0011h,0022h,0033h
 
 	.text  
START: 	
	LDP 	#0
    SETC 	INTM           	;Disable all interrupts
	SPLK 	#0000H, IMR	    ;Mask all core ints
	LACC 	IFR				;Read Interrupt flags
	SACL 	IFR				;Clear all ints flags
	CLRC 	SXM           	;Clear Sign Extension Mode
	CLRC 	OVM           	;Reset Overflow Mode
	SETC 	CNF            	;Config Block B0 to Data mem.

	LDP 	#00E0h
	SPLK 	#002Fh, WDCR    	;Enable Interal Watchdog
	KICK_DOG    
	
	LDP 	#0
	SPLK 	#0h, GPR0       	;Set wait state generator for:
	OUT 	GPR0, WSGR      	;Program Space, 0-7 wait states
	LDP 	#00E0h
	SPLK 	#0000h,SCSR    	;CLKOUT=CPUCLK

	LDP 	#OCRA>>7	    	;Get the OCRA Register offset address
	SPLK 	#0000h,  OCRA		;IOPA,IOPB as I/O port 
	SPLK 	#02C3h,  OCRB		;IOPC6-7,CANTX,CANRX ,IOPD1 as Interrupt
	SPLK 	#0FF00h, PADATDIR	;PORT A ,all as output low 
	SPLK 	#0FF00h, PBDATDIR	;PORT B ,all as output low  	
	SPLK 	#3F30h,  PCDATDIR	;PORT C, all as output low except CAN
	SPLK	#0100h,  PDDATDIR   ;PORT D, IOPD-0,output,IOPD-1 input

	LDP		#EVIMRC>>7		
	SPLK    #0, EVIMRC		;CAP0-2 Disable	
	SPLK	#1, EVIMRB		;GP Timer 2 period interrupt enabled
	SPLK	#0101011101000100b, T2CON; clk = 16Mhz/128 (125k)
					;010 Stop after current timer period is complete on emulation suspend
					;10 Continuous up-count mode
					;111 x/128
					;0 Use own TENABLE BIT
					;1 Enable timer operations
					;00 Internal clk
					;01 LD CMPR When counter value is 0 or equals period register value
					;0 Disable timer compare operation
					;0 use own period register
	SPLK	#0000h,  GPTCON
	SPLK	#0ffffh, T2PR		; period = 65536 (0.5s approx)

	LDP 	#XINT1CR>>7
	SPLK 	#0005h, XINT1CR	;rising edge int, High prority, Enable Xint1 interrupt
	SPLK 	#0005h, XINT2CR ;rising edge int, High prority, Enable Xint2 interrupt

	LDP #0
	SPLK #0005H,IMR		;Enable Can,Xint1,xint2(int1) & timer 2 interrupt (int3)	
	
	call    SetCan 
	
	CLRC    INTM
	OnLed
		
LOOP:   
	ClrWDI
	NOP 
	NOP 
	IDLE
	NOP 
	NOP
	SetWDI
	NOP
	NOP
	B LOOP	
	 
PHANTOM:
	KICK_DOG        		;Resets WD counter
    B PHANTOM 
;/////////////////////////////////////////////
GISR1:
	NOP
	RET
GISR3:
	NOP
	RET