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📄 lcddram.lst

📁 最先进的信号机程序,经过很多重要场合测试通过
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 311   4                                               cpu_fpga_set(0x94,0x5122,289);
 312   4                                               }
 313   3      
 314   3                             break;
 315   3                  case 0x95:j=(idcode-1)*98;      //设置阶段表
 316   3                             for(i=0;i<98;i++){
 317   4                                   if(i==4){
 318   5                                           do{}while(busy==0);XBYTE[0x5242+i+j]=XBYTE[0XC410+i]-1;
 319   5                                           }else{
 320   5                                                do{}while(busy==0);XBYTE[0x5242+i+j]=XBYTE[0XC410+i];
 321   5                                                 }
 322   4      
 323   4                                               }
 324   3      
 325   3                            do{}while(busy==0);
 326   3                            XBYTE[0XC409]=0;
 327   3                            cpu_fpga_set(0x95,0x5242+j,98);            //发送到fpga
 328   3                            break;
 329   3                  case 0x96:j=(idcode-1)*41;      //设置控制方案
 330   3                             for(i=0;i<41;i++){
 331   4      
 332   4                                   do{}while(busy==0);XBYTE[0x5e82+i+j]=XBYTE[0XC410+i];
 333   4      
 334   4                                               }
 335   3                             do{}while(busy==0);XBYTE[0XC409]=0;
 336   3                             cpu_fpga_set(0x96,0x5e82+j,41);            //发送到fpga
 337   3                             break;
 338   3                 // case 0x97:break;
 339   3                  case 0x98:j=(idcode-1)*74;      //设置计划
 340   3                             for(i=0;i<74;i++){
 341   4                                  do{}while(busy==0);XBYTE[0x63A2+i+j]=XBYTE[0XC410+i];
 342   4                                              }
 343   3                             XBYTE[0XC409]=0;
 344   3                             cpu_fpga_set(0x98,0x63a2+j,74);            //发送到fpga
 345   3                             break;
 346   3                  case 0x99: j=XBYTE[0XC40c];
 347   3                             j=(j-1)*6;
 348   3                             for(i=0;i<6;i++){  //设置日计划调度表
 349   4                                  do{}while(busy==0);XBYTE[0x6cE2+i+j]=XBYTE[0XC410+i];
 350   4                                              }
 351   3                             do{}while(busy==0);XBYTE[0XC409]=0;
 352   3                             cpu_fpga_set(0x99,0x6ce2,60);            //发送到fpga
 353   3                             break;
 354   3              //    case 0x9a:break;
 355   3              //    case 0x9b:break;
 356   3              //    case 0x9c:break;
 357   3              //    case 0x9d:break;
 358   3                    case 0x9e://do{}while(busy==0);XBYTE[0XC410]=0xde;    //遥控阶段对应表
 359   3                              do{}while(busy==0);XBYTE[0X6d28]=XBYTE[0XC410];
 360   3                              do{}while(busy==0);XBYTE[0X6d29]=XBYTE[0XC411];
 361   3      
 362   3                              do{}while(busy==0);XBYTE[0XC409]=0;
C51 COMPILER V6.02  LCDDRAM                                                                08/02/2006 14:44:14 PAGE 7   

 363   3                              break;
 364   3                    case 0x9f://do{}while(busy==0);XBYTE[0XC410]=0xde;    //遥控阶段对应表
 365   3                              do{}while(busy==0);XBYTE[0X6d20]=XBYTE[0XC410];
 366   3                              do{}while(busy==0);XBYTE[0X6d21]=XBYTE[0XC411];
 367   3                              do{}while(busy==0);XBYTE[0X6d22]=XBYTE[0XC412];
 368   3                              do{}while(busy==0);XBYTE[0X6d23]=XBYTE[0XC413];
 369   3                              do{}while(busy==0);XBYTE[0X6d24]=XBYTE[0XC414];
 370   3                              do{}while(busy==0);XBYTE[0X6d25]=XBYTE[0XC415];
 371   3                              do{}while(busy==0);XBYTE[0X6d26]=XBYTE[0XC416];
 372   3                              do{}while(busy==0);XBYTE[0X6d27]=XBYTE[0XC417];
 373   3                              do{}while(busy==0);XBYTE[0XC409]=0;
 374   3                              break;
 375   3                  default:break;
 376   3                    }
 377   2      
 378   2          }
 379   1        return 1;
 380   1      }
C51 COMPILER V6.02  LCDDRAM                                                                08/02/2006 14:44:14 PAGE 8   

NAME                                    CLASS   MSPACE  TYPE    OFFSET  SIZE
====                                    =====   ======  ====    ======  ====


P1 . . . . . . . . . . . . . . . . . .  SFR      DATA   U_CHAR   0090H  1
tr_flagaddr. . . . . . . . . . . . . .  EXTERN   XDATA  U_INT    -----  2
T0 . . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      00B4H  1
AC . . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      00D6H  1
T1 . . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      00B5H  1
EA . . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      00AFH  1
RD . . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      00B7H  1
ES . . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      00ACH  1
RI . . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      0098H  1
INT0 . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      00B2H  1
CY . . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      00D7H  1
TI . . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      0099H  1
INT1 . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      00B3H  1
led82. . . . . . . . . . . . . . . . .  EXTERN   XDATA  ARRAY    -----  5
led83. . . . . . . . . . . . . . . . .  EXTERN   XDATA  ARRAY    -----  30
PS . . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      00BCH  1
step_counter . . . . . . . . . . . . .  EXTERN   XDATA  U_CHAR   -----  1
OV . . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      00D2H  1
WR . . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      00B6H  1
utemp. . . . . . . . . . . . . . . . .  PUBLIC   XDATA  U_INT    0000H  2
IE0. . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      0089H  1
IE1. . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      008BH  1
busy . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      0095H  1
ET0. . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      00A9H  1
ET1. . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      00ABH  1
TF0. . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      008DH  1
TF1. . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      008FH  1
RB8. . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      009AH  1
ttd. . . . . . . . . . . . . . . . . .  PUBLIC   XDATA  U_CHAR   0002H  1
EX0. . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      00A8H  1
IT0. . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      0088H  1
TB8. . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      009BH  1
EX1. . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      00AAH  1
IT1. . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      008AH  1
P. . . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      00D0H  1
SM0. . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      009FH  1
SM1. . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      009EH  1
SM2. . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      009DH  1
deal_lcddram . . . . . . . . . . . . .  PUBLIC   CODE   PROC     0000H  -----
  flag . . . . . . . . . . . . . . . .  * REG *  DATA   U_CHAR   0003H  1
  id . . . . . . . . . . . . . . . . .  * REG *  DATA   U_CHAR   0002H  1
  idcode . . . . . . . . . . . . . . .  AUTO     XDATA  U_CHAR   0000H  1
  i. . . . . . . . . . . . . . . . . .  AUTO     XDATA  U_INT    0001H  2
  j. . . . . . . . . . . . . . . . . .  AUTO     XDATA  U_INT    0003H  2
PT0. . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      00B9H  1
PT1. . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      00BBH  1
RS0. . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      00D3H  1
TR0. . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      008CH  1
RS1. . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      00D4H  1
TR1. . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      008EH  1
_cpu_fpga_set. . . . . . . . . . . . .  PUBLIC   CODE   PROC     0000H  -----
  flag . . . . . . . . . . . . . . . .  * REG *  DATA   U_CHAR   0001H  1
  ptr. . . . . . . . . . . . . . . . .  AUTO     XDATA  U_INT    0000H  2
  len. . . . . . . . . . . . . . . . .  AUTO     XDATA  U_INT    0002H  2
  i. . . . . . . . . . . . . . . . . .  AUTO     XDATA  U_INT    0004H  2
PX0. . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      00B8H  1
PX1. . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      00BAH  1
C51 COMPILER V6.02  LCDDRAM                                                                08/02/2006 14:44:14 PAGE 9   

NAME                                    CLASS   MSPACE  TYPE    OFFSET  SIZE
====                                    =====   ======  ====    ======  ====


REN. . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      009CH  1
data_address . . . . . . . . . . . . .  EXTERN   XDATA  U_INT    -----  2
tt . . . . . . . . . . . . . . . . . .  PUBLIC   XDATA  U_CHAR   0003H  1
address. . . . . . . . . . . . . . . .  EXTERN   XDATA  U_INT    -----  2
RXD. . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      00B0H  1
step_num . . . . . . . . . . . . . . .  EXTERN   XDATA  U_CHAR   -----  1
TXD. . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      00B1H  1
F0 . . . . . . . . . . . . . . . . . .  ABSBIT   -----  BIT      00D5H  1


MODULE INFORMATION:   STATIC OVERLAYABLE
   CODE SIZE        =   3855    ----
   CONSTANT SIZE    =   ----    ----
   XDATA SIZE       =      4      11
   PDATA SIZE       =   ----    ----
   DATA SIZE        =   ----    ----
   IDATA SIZE       =   ----    ----
   BIT SIZE         =   ----    ----
END OF MODULE INFORMATION.


C51 COMPILATION COMPLETE.  0 WARNING(S),  0 ERROR(S)

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