main3.nm

FPGA flash 编程序,使用CYCLONE和FLASH

00000060 A na_led_pio
00000060 A nasys_pio_0
00000070 A na_sysid
00000078 A na_jtag_uart
00000078 A na_sysid_end
00000080 A na_jtag_uart_end
00000080 A na_pll_0
00000080 a np_epcscontrol_irrdy_mask
00000080 a np_epcscontrol_irrdy_mask
00000080 a np_epcsstatus_rrdy_mask
00000080 a np_epcsstatus_rrdy_mask
00000080 a np_uartcontrol_irrdy_mask
00000080 a np_uartcontrol_irrdy_mask
00000080 a np_uartstatus_rrdy_mask
00000080 a np_uartstatus_rrdy_mask
000000a0 A na_pll_0_end
000000b9 a na_epcs_dp
000000b9 a na_epcs_dp
000000c7 a na_epcs_be
000000c7 a na_epcs_be
000000d8 a na_epcs_se
000000d8 a na_epcs_se
00000100 a na_epcs_page_size
00000100 a na_epcs_page_size
00000100 a np_epcscontrol_ie_mask
00000100 a np_epcscontrol_ie_mask
00000100 a np_epcsrxdata
00000100 a np_epcsrxdata
00000100 a np_epcsstatus_e_mask
00000100 a np_epcsstatus_e_mask
00000100 a np_uartcontrol_ie_mask
00000100 a np_uartcontrol_ie_mask
00000100 a np_uartstatus_e_mask
00000100 a np_uartstatus_e_mask
00000101 a np_epcstxdata
00000101 a np_epcstxdata
00000102 a np_epcsstatus
00000102 a np_epcsstatus
00000103 a np_epcscontrol
00000103 a np_epcscontrol
00000104 a np_epcsreserved
00000104 a np_epcsreserved
00000105 a np_epcsslaveselect
00000105 a np_epcsslaveselect
00000106 a np_epcsendofpacket
00000106 a np_epcsendofpacket
00000200 a np_epcscontrol_ieop_mask
00000200 a np_epcscontrol_ieop_mask
00000200 a np_epcsstatus_eop_mask
00000200 a np_epcsstatus_eop_mask
00000200 a np_uartcontrol_tbrk_mask
00000200 a np_uartcontrol_tbrk_mask
00000300 A na_cs8900_0
00000320 A na_cs8900_0_end
00000400 a nasys_dcache_size
00000400 a nasys_dcache_size
00000400 a np_epcscontrol_sso_mask
00000400 a np_epcscontrol_sso_mask
00000400 a np_uartcontrol_eop_mask
00000400 a np_uartcontrol_eop_mask
00000400 a np_uartstatus_dcts_mask
00000400 a np_uartstatus_dcts_mask
00000800 A na_idt7132
00000800 A na_idt7132_size
00000800 A nasys_main_flash_size
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00000800 a nasys_icache_size
00000800 a np_uartstatus_cts_mask
00000800 a np_uartstatus_cts_mask
00001000 A na_idt7132_end
00001000 A na_onchip_rom
00001000 A na_onchip_rom_size
00001000 a np_uartstatus_eop_mask
00001000 a np_uartstatus_eop_mask
00002000 A na_epcs_controller
00002000 A na_onchip_rom_end
00002000 A nasys_epcs_0
00002000 A nasys_main_flash
00002000 A nasys_reset_address
00002800 A na_cpu_jtag_debug_module
00002800 A nasys_main_flash_end
00002820 A nasys_break_address
0000c350 A nasys_clock_freq_1000
00010000 a na_epcs_sector_size
00010000 a na_epcs_sector_size
00080000 a na_epcs_bulk_size
00080000 a na_epcs_bulk_size
000fff60 A nasys_data_mem_size
000fff60 A nasys_program_mem_size
00100000 A na_ext_ram
00100000 A na_ext_ram_size
00100020 A nasys_exception_address
001000a0 A nasys_data_mem
001000a0 A nasys_program_mem
001000a0 T __reset
001000a0 T _start
001000ac t text_init
001000c4 t data_init
001000f8 t crt0_end
001000fc t wait_tiny
00100134 T sst39vf160_flash_write_16
001001d4 T nr_flash_write_hw
001001e4 T nr_flash_erase_block
00100274 T nr_flash_erase_sector
00100280 T nr_flash_erase_sector_4kB
00100320 T nr_flash_erase
001003c8 T nr_flash_write
001003d8 T nr_flash_write_buffer
001004ec T delay
001004fc T Transmit485
00100500 T TransmitEnternet
00100504 T Check_Ram_Write
00100528 T Write_Comm_to_Ram
00100738 T Check_Ram_Read
0010075c T Check_Frame
00100858 T Check_Transparence
00100958 T Add_transparences
00100a08 T Cal_Crc
00100a7c T TransmitTestPackage
00100c68 T myisr
00100cd0 T ReceiveISRUart1
00100d3c T Check_Tx_Mark_Bit
00100e98 T Handle_Para
00100f90 T Write_Ram
00100f94 T Write_Flash_Flow
001010dc T Write_Flash
00101d10 T Write_Comm
00101fa4 T TransmitComm
00102048 T Transmit_Flow_Package
0010223c T Transmit_Query_Package
001025c8 T Transmit_Answer_Package
001027e8 T Transmit_Lai_Package
001029d8 T Transmit_Mistake_Package
00102bac T ReceiveComm
00103178 T main
001035c0 T Receive485
001035c4 T ReceiveEnternet
001035c8 T __mulsi3
001035f0 T memcpy
001036ac T call_functions
001036ec T alt_main
00103760 T nr_delay
00103764 t delay_specified_milliseconds
0010376c t delay_one_millisecond
00103780 T _nr_isr_handler
0010387c T nr_installuserisr2
001038ec T nr_installuserisr
001038f8 T nr_setirqenable
00103928 T nr_uart_initialize
0010392c T nr_uart_rxchar
0010394c T nr_uart_txchar
00103964 T nr_uart_txcr
00103994 T nr_uart_txhex16
00103a08 T nr_uart_txhex32
00103a44 T nr_uart_txhex
00103a50 T nr_uart_txstring
00103a88 T _nr_ensure_isr_jmp
00103ad8 t jmp_to_isr_funnel
00103ae4 t isr_funnel
00103b9c t software_exception
00103ba0 ? _ctors_begin
00103ba0 ? _ctors_end
00103ba0 ? _dtors_begin
00103ba0 ? _dtors_end
00103ba0 A _etext
00103ba0 A _nasys_rodata
00103c2d A _nasys_data_destination
00103c2d A _nasys_data_source
00103c2d A _nasys_rodata_end
00103c2d D _data
00103c30 D _nasys_data_destination_end
00103c30 G nnn
00103c34 G ledd
00103c38 G leddata
00103c3c G Data_Number
00103c40 G Now_MarkRx_Number
00103c44 G BeginBitContent
00103c48 G RevStatus
00103c4c G First
00103c50 G RxTail
00103c54 G RxHead
00103c58 G alt_envp
00103c5c G alt_argv
00103c60 G alt_argc
00103c64 A __bss_start
00103c64 A _edata
00103c64 A _nasys_data_source_end
00103c64 A _nasys_uninitialized_storage
00103c64 S jj
00103c68 S ResetNumber
00103c6c S Parameter
00103c70 S WriteGate1
00103c74 S WriteGate2
00103c78 S CheckByte_Write
00103c7a S CheckByte_Read
00103c7c S Now_Tail_High
00103c80 S Now_Tail_Low
00103c84 S Now_Tail_Add
00103c88 S Now_Head_Add
00103c8c S Now_Ram_Write_Add
00103c90 S Now_Ram_Read_Add
00103c94 S Now_Ram_Read_End_Add
00103c98 S Rx_Head_High_test
00103c99 S Rx_Head_Low_test
00103c9a S Rx_Tail_High_test
00103c9b S Rx_Tail_Low_test
00103c9c S Now_Tail_High_test
00103c9d S Now_Tail_Low_test
00103ca0 S Conf_Phase1_Address_Flash
00103ca4 S Conf_Phase2_Address_Flash
00103ca8 S Conf_Stage_Address_Flash
00103cac S Conf_Controlstage_Address_Flash
00103cb0 S Conf_Daydesign_Address_Flash
00103cb4 S Conf_Daydesigntable_Address_Flash
00103cb8 S Conf_Phase1_Address_Backup
00103cbc S Conf_Phase2_Address_Backup
00103cc0 S Conf_Stage_Address_Backup
00103cc4 S Conf_Controlstage_Address_Backup
00103cc8 S Conf_Daydesign_Address_Backup
00103ccc S Conf_Daydesigntable_Address_Backup
00103cd0 S Flow_Information_Base
00103cd4 S Flow_Information_End
00103cd8 S Now_Flow_Information_Add
00103cdc S WrRamTimePhase
00103cdd S Receive_From
00103cde S Finished_Receive
00103cdf S Transmit_Number
00103ce0 S transparence
00103ce4 S transparence_valid
00103ce8 S Valid_Data
00103ce9 S Valid_Data_Number
00103cea S Test_Bit
00103cec S Direct_Now_Data_Length
00103cf0 S Check_Temp
00103cf2 S Add_Bit
00103cf4 S Add_transparence
00103cf8 S Add_transparence_valid
00103cfc S Flash_Bit
00103d00 S uart_use
00103d04 S Flash_Add_Sh
00103d08 S Phase_Number
00103d09 S Time_Phase
00103d0a S aaa
00103d0c S bbb
00103d10 B _bss
00103d10 b irq_context
00103d90 b irq_handler
00103e10 B Flash__Scheme_First
00103e28 B Rx_Tail_High
00103e40 B Tx_Head_High
00103e58 B Tx_Tail_High
00103e70 B Rx_Tail_Low
00103e88 B Conf_Phase1_Address_Buffer
00103fa8 B Tx_Head_Low
00103fc0 B Conf_Stage_Address_Buffer
00104024 B MarkTx
0010403c B Test_Package_Data
0010404c B Rx_Head_High
00104064 B Conf_Daydesigntable_Address_Buffer
001040a0 B Conf_Controlstage_Address_Buffer
001040c9 B RxBuf
001041c8 B Conf_Phase2_Address_Buffer
001042e8 B Conf_Daydesign_Address_Buffer
00104332 B CheckData
0010458a B Green_Phase
0010459c B Tx_Tail_Low
001045b4 B Rx_Head_Low
001045cc A _end
001045cc A _nasys_uninitialized_storage_end
0010bc20 A _gp
00200000 A na_cfi_flash_0
00200000 A na_cfi_flash_0_size
00200000 A na_ext_ram_end
00200000 A nasys_data_mem_end
00200000 A nasys_program_mem_end
00200000 A nasys_stack_top
00400000 A na_cfi_flash_0_end
02faf080 A nasys_clock_freq