flash.c

FPGA flash 编程序,使用CYCLONE和FLASH

/*
  file: flash(am29lv160).c
  modified by liangqi
   2006-03-25
*/


#include "nios.h"
#include "excalibur.h"

// ---------------------------------------------
// Private Routines

// This routine actually takes about 3 us on a 33.2aaaMHz Nios32.
static wait_tiny(int x_us)
{
  for(;x_us>0;x_us--)
  {
	  volatile unsigned long iTimeout = 50000/8250;//nasys_clock_freq_1000 / 8250;
	  while (iTimeout--)
	  {
	    ;
	  }
	}
}



// Write val to the given flash address.
// Return value: 0 on success, -1 on failure.
int sst39vf160_flash_write_16 (
    unsigned short *flash_base,
    unsigned short *addr,
    unsigned short val  )
{
  volatile unsigned short *fb = flash_base;
  volatile unsigned short *a = addr;
  unsigned short us1, us2;
  int result = 0;
na_uart1->np_uartcontrol=0;
#ifdef nasys_main_flash
  if (-1 == (int)fb)
    fb = nasys_main_flash;
#endif // nasys_main_flash

  fb[0x555] = 0xAA; // 1st cycle  addr = 0x5555, data = AA
  fb[0x2aa] = 0x55; // 2nd cycle  addr = 0x2aaa, data = 55
  fb[0x555] = 0xA0; // 3rd cycle  addr = 0x5555, data = A0

 
  *a = val;     // 4th cycle  addr = PA, data = PD

  // Delay 40us
  wait_tiny(45);

  us1 = *a;
  if (us1 != val)
    result = -1;
na_uart1->np_uartcontrol=np_uartcontrol_irrdy_mask;
  return result;
}

// ---------------------------------------------
// Public Routines

// Write val to the given flash address.
// Return value: 0 on success, -1 on failure.
int nr_flash_write_hw (
    unsigned short *flash_base,
    unsigned short *addr,
    unsigned short val  )
{

  return (sst39vf160_flash_write_16(flash_base,addr,val));
}

// Erase the flash sector at sector_address.
// Return value: 0 on success, -1 on failure.

int nr_flash_erase_sector (
      unsigned short *flash_base,
      unsigned short *sector_address  )
{
	return(nr_flash_erase_block(flash_base,sector_address));
}
	

int nr_flash_erase_block  (
      unsigned short *flash_base,
      unsigned short *sector_address  )
{
  volatile unsigned short *fb = (unsigned short *) flash_base;
  volatile unsigned short *sa = (unsigned short *) sector_address;
  int result=0;

#ifdef nasys_main_flash
  if (-1 == (int)fb)
    fb = nasys_main_flash;
#endif // nasys_main_flash

  fb[0x555] = 0xAA; // 1st cycle  addr = 5555, data = AA
  fb[0x2aa] = 0x55; // 2nd cycle  addr = 2aaa, data = 55
  fb[0x555] = 0x80; // 3rd cycle  addr = 5555, data = 80
  fb[0x555] = 0xAA; // 4th cycle  addr = 5555, data = AA
  fb[0x2aa] = 0x55; // 5th cycle  addr = 2aaa, data = 55

  *sa = 0x30; // 6th cycle  addr = XXX, data = 50

  // Delay 50ms
  nr_delay(50);

  if (0xFF != *sa)  // done? note: 8bit data
    result = -1;	// erase error

  return result;
}


int nr_flash_erase_sector_4kB  (
      unsigned short *flash_base,
      unsigned short *sector_address  )
{
  volatile unsigned short *fb = (unsigned short *) flash_base;
  volatile unsigned short *sa = (unsigned short *) sector_address;
  int result=0;

na_uart1->np_uartcontrol=0;

#ifdef nasys_main_flash
  if (-1 == (int)fb)
    fb = nasys_main_flash;
#endif // nasys_main_flash

  fb[0x555] = 0xAA; // 1st cycle  addr = 5555, data = AA
  fb[0x2aa] = 0x55; // 2nd cycle  addr = 2aaa, data = 55
  fb[0x555] = 0x80; // 3rd cycle  addr = 5555, data = 80
  fb[0x555] = 0xAA; // 4th cycle  addr = 5555, data = AA
  fb[0x2aa] = 0x55; // 5th cycle  addr = 2aaa, data = 55

  *sa = 0x30; // 6th cycle  addr = XXX, data = 30

  // Delay 50ms
  nr_delay(100);

  if (0xFF != *sa)  // done? note: 8bit data
    result = -1;	// erase error

na_uart1->np_uartcontrol=np_uartcontrol_irrdy_mask;
  return result;
}


// Erase the entire flash.
// Return value: 0 on success, -1 on failure.

int nr_flash_erase(unsigned short *flash_base)
{
  volatile unsigned char *fb = (unsigned char*) flash_base;
  int result = 0;

#ifdef nasys_main_flash
  if (-1 == (int)fb)
  {
    fb = nasys_main_flash;
  }
#endif // nasys_main_flash

  //result = erase_flash_single_command(fb);
	// Erase the entire flash in one command. AKA CHIP ERASE sst39vf160
  fb[0x555] = 0xAA; // 1st cycle  addr = 0x5555, data = AA
  fb[0x2aa] = 0x55; // 2nd cycle  addr = 0x2aaa, data = 55
  fb[0x555] = 0x80; // 3rd cycle  addr = 0x5555, data = 80
  fb[0x555] = 0xAA; // 4th cycle  addr = 0x5555, data = AA
  fb[0x2aa] = 0x55; // 5th cycle  addr = 0x2aaa, data = 55
  fb[0x555] = 0x10; // 6th cycle  addr = 0x5555, data = 10

  //Delay 200ms
  nr_delay(200);
  
  if(0xff == *fb)
  	result = -1;
  
  return result;
}


int nr_flash_write (
		unsigned short *flash_base,
    unsigned short *addr,
    unsigned short val    )
{
	return(sst39vf160_flash_write_16 (flash_base, addr,   val));
}

/**
// Return value: 0 on success, -1 on failure.
// Note: the integer "size" is given as a number of half-words to 
// write.   How convenient.  We write this 8-bit-wide flash one byte
// at a time (of course).
int nr_flash_write_buffer    (
    unsigned short *flash_base,
    unsigned short *start_address,
    unsigned short *buffer,
    int size    )
{
  volatile unsigned short *fb = flash_base;
  int i;
  int result = 0;

#ifdef nasys_main_flash
  if (-1 == (int)fb)
    fb = nasys_main_flash;
#endif // nasys_main_flash

  
  for (i = 0; i < size; ++i)
  {

    result =  sst39vf160_flash_write_16(flash_base, start_address+i, buffer[i]);
    if(result)  
      break;
  }

  return result;
}
*/

static void unlock_bypass_mode(volatile unsigned short *flash_base)
{ // 065d
  flash_base[0x555] = 0xAA; // unlock bypass command - cycle 1
  flash_base[0x2AA] = 0x55; // unlock bypass command - cycle 2
  flash_base[0x555] = 0x20; // unlock bypass command - cycle 3
}

// Turn bypass mode off, disabling fast writes and enabling normal function.
static void reset_bypass_mode(volatile unsigned short *flash_base)
{
  *flash_base = 0x90; // exit unlock bypass reset command - cycle 1
  *flash_base = 0x0;  // exit unlock bypass reset command - cycle 2
}

static void flash_reset(volatile unsigned short *flash_base)
{
   *flash_base=0xf0;
}

static int nr_flash_write_bypass(volatile unsigned short *flash_base,
  volatile unsigned short *addr, unsigned short val)
{
  unsigned short us1, us2;
  int iTimeout;
  int result = 0;
na_uart1->np_uartcontrol=0;
  nm_dcache_invalidate_line(addr);
  nm_icache_invalidate_line(addr);

  *flash_base = 0xA0;   // unlock bypass program command - 1st cycle
  *addr = val;          // program address and data    - 2nd cycle
   
   wait_tiny(50);
  //result = await_write_complete(addr,val);
  if(result)
    return result;

  us1 = *addr;
 // ggg = *addr;
 // ddd = val;

  if (us1 != val)
    result = -1;

  return result;
na_uart1->np_uartcontrol=np_uartcontrol_irrdy_mask;
}

int nr_flash_write_buffer
    (
    unsigned short *flash_base,
    unsigned short *start_address,
    unsigned short *buffer,
    int size
    )
{
  volatile unsigned short *fb  = (unsigned short *) flash_base;
                 unsigned short *sa  = (unsigned short *) start_address;
                 unsigned short *buf = (unsigned short *) buffer;
       
  int i;
  int result = 0;
na_uart1->np_uartcontrol=0;
#ifdef nasys_main_flash
  if (-1 == (int)fb)
    fb = nasys_main_flash;
#endif // nasys_main_flash

  unlock_bypass_mode(fb);
  for (i = 0; i < size; ++i)
  {
    result = nr_flash_write_bypass(fb, sa + i, buf[i]);
    if(result)
      break;

  }
  reset_bypass_mode(fb);

  return result;
na_uart1->np_uartcontrol=np_uartcontrol_irrdy_mask;
}