main3.objdump

FPGA flash 编程序,使用CYCLONE和FLASH

		unsigned short *flash_base,
    unsigned short *addr,
    unsigned short val    )
{
	return(sst39vf160_flash_write_16 (flash_base, addr,   val));
  100364:	31bfffcc 	andi	r6,r6,65535
  100368:	02000434 	movhi	r8,16
  10036c:	42003f04 	addi	r8,r8,252
  100370:	4000683a 	jmp	r8

00100374 <nr_flash_write_buffer>:
}

/**
// Return value: 0 on success, -1 on failure.
// Note: the integer "size" is given as a number of half-words to 
// write.   How convenient.  We write this 8-bit-wide flash one byte
// at a time (of course).
int nr_flash_write_buffer    (
    unsigned short *flash_base,
    unsigned short *start_address,
    unsigned short *buffer,
    int size    )
{
  volatile unsigned short *fb = flash_base;
  int i;
  int result = 0;

#ifdef nasys_main_flash
  if (-1 == (int)fb)
    fb = nasys_main_flash;
#endif // nasys_main_flash

  
  for (i = 0; i < size; ++i)
  {

    result =  sst39vf160_flash_write_16(flash_base, start_address+i, buffer[i]);
    if(result)  
      break;
  }

  return result;
}
*/

static void unlock_bypass_mode(volatile unsigned short *flash_base)
{ // 065d
  flash_base[0x555] = 0xAA; // unlock bypass command - cycle 1
  flash_base[0x2AA] = 0x55; // unlock bypass command - cycle 2
  flash_base[0x555] = 0x20; // unlock bypass command - cycle 3
}

// Turn bypass mode off, disabling fast writes and enabling normal function.
static void reset_bypass_mode(volatile unsigned short *flash_base)
{
  *flash_base = 0x90; // exit unlock bypass reset command - cycle 1
  *flash_base = 0x0;  // exit unlock bypass reset command - cycle 2
}

static void flash_reset(volatile unsigned short *flash_base)
{
   *flash_base=0xf0;
}

static wait_at_least_1_us(void)
{
  volatile unsigned long iTimeout = 2;//20000/8250;//nasys_clock_freq_1000 / 8250;
  while (iTimeout--)
  {
    ;
  }
}
// Read the given address until two successive reads yield the
// same value.
// Return value: 0 on success, -1 on timeout failure.
static int await_write_complete(volatile unsigned short *addr, const unsigned short correct_value)
{
  // The "typical" time for a word write is 11 us.
  // Set a timeout of about 4 times "typical".
        //
        // TPA 2/14/2003: Read that datasheet more carefully!
        //                The *Maximum* programming time is 150us.
        //                Waiting several times the maximum time
        //                seems like a much better idea than giving-up
        //                well before the published spec says we
        //                should.
        //
  unsigned long iTimeout = 1500;
  int return_value = -1; // Pessimistic return value.

  while (iTimeout)
  {
    wait_at_least_1_us();

    // While the flash is working on program data, read accesses return
    // "status" instead of data.  Status bit 7 is the complement of the
    // data being written.  When the program operation is complete and
    // successful, the written data is returned.  So, read the written
    // address until it equals the data written.

    if (*addr == correct_value)
      break;
    iTimeout--;
  }

  if (iTimeout)
    return_value = 0;

  return return_value;
}

static int nr_flash_write_bypass(volatile unsigned short *flash_base,
  volatile unsigned short *addr, unsigned short val)
{
  unsigned short us1, us2;
  int iTimeout;
  int result = 0;
//na_uart1->np_uartcontrol=0;
  nm_dcache_invalidate_line(addr);
  nm_icache_invalidate_line(addr);

  *flash_base = 0xA0;   // unlock bypass program command - 1st cycle
  *addr = val;          // program address and data    - 2nd cycle
   
 //  wait_tiny(50);
  result = await_write_complete(addr,val);
//  if(result)
//    return result;

 // us1 = *addr;
 // ggg = *addr;
 // ddd = val;

//  if (us1 != val)
//    result = -1;

  return result;
//na_uart1->np_uartcontrol=np_uartcontrol_irrdy_mask;
}

int nr_flash_write_buffer
    (
    unsigned short *flash_base,
    unsigned short *start_address,
    unsigned short *buffer,
    int size
    )
{
  100374:	defffe04 	addi	sp,sp,-8
  volatile unsigned short *fb  = (unsigned short *) flash_base;
  100378:	201b883a 	mov	r13,r4
                 unsigned short *sa  = (unsigned short *) start_address;
                 unsigned short *buf = (unsigned short *) buffer;
       
  int i;
  int result = 0;
//na_uart1->np_uartcontrol=0;
#ifdef nasys_main_flash
  if (-1 == (int)fb)
  10037c:	023fffc4 	movi	r8,-1
  100380:	dc000115 	stw	r16,4(sp)
  100384:	0009883a 	mov	r4,zero
  100388:	6a002d26 	beq	r13,r8,100440 <nr_flash_write_buffer+0xcc>
  10038c:	00802a84 	movi	r2,170
  100390:	6882aaad 	sthio	r2,2730(r13)
  100394:	00c01544 	movi	r3,85
  100398:	68c1552d 	sthio	r3,1364(r13)
  10039c:	00800804 	movi	r2,32
  1003a0:	6882aaad 	sthio	r2,2730(r13)
    fb = nasys_main_flash;
#endif // nasys_main_flash

  unlock_bypass_mode(fb);
  for (i = 0; i < size; ++i)
  1003a4:	0019883a 	mov	r12,zero
  1003a8:	01c01e0e 	bge	zero,r7,100424 <nr_flash_write_buffer+0xb0>
  1003ac:	4015883a 	mov	r10,r8
  1003b0:	681f883a 	mov	r15,r13
  1003b4:	04002804 	movi	r16,160
  1003b8:	02c00084 	movi	r11,2
  1003bc:	6305883a 	add	r2,r12,r12
  1003c0:	1187883a 	add	r3,r2,r6
  1003c4:	1900000b 	ldhu	r4,0(r3)
  1003c8:	1153883a 	add	r9,r2,r5
  1003cc:	4800003b 	flushd	0(r9)
  1003d0:	4800603a 	flushi	r9
  1003d4:	7c00002d 	sthio	r16,0(r15)
  1003d8:	4900002d 	sthio	r4,0(r9)
  1003dc:	02017704 	movi	r8,1500
  1003e0:	03bfffc4 	movi	r14,-1
  1003e4:	dac00035 	stwio	r11,0(sp)
  1003e8:	d8800037 	ldwio	r2,0(sp)
  1003ec:	10bfffc4 	addi	r2,r2,-1
  1003f0:	d8800035 	stwio	r2,0(sp)
  1003f4:	d8c00037 	ldwio	r3,0(sp)
  1003f8:	1abffb1e 	bne	r3,r10,1003e8 <nr_flash_write_buffer+0x74>
  1003fc:	4880002b 	ldhuio	r2,0(r9)
  100400:	10bfffcc 	andi	r2,r2,65535
  100404:	11001026 	beq	r2,r4,100448 <nr_flash_write_buffer+0xd4>
  100408:	423fffc4 	addi	r8,r8,-1
  10040c:	403ff51e 	bne	r8,zero,1003e4 <nr_flash_write_buffer+0x70>
  {
    result = nr_flash_write_bypass(fb, sa + i, buf[i]);
    if(result)
  100410:	7005003a 	cmpeq	r2,r14,zero
  100414:	7009883a 	mov	r4,r14
  100418:	10000226 	beq	r2,zero,100424 <nr_flash_write_buffer+0xb0>
  10041c:	63000044 	addi	r12,r12,1
  100420:	61ffe616 	blt	r12,r7,1003bc <nr_flash_write_buffer+0x48>
  100424:	00802404 	movi	r2,144
  100428:	6880002d 	sthio	r2,0(r13)
      break;

  }
  reset_bypass_mode(fb);

  return result;
//na_uart1->np_uartcontrol=np_uartcontrol_irrdy_mask;
}
  10042c:	2005883a 	mov	r2,r4
  100430:	6800002d 	sthio	zero,0(r13)
  100434:	dc000117 	ldw	r16,4(sp)
  100438:	dec00204 	addi	sp,sp,8
  10043c:	f800283a 	ret
  100440:	03480004 	movi	r13,8192
  100444:	003fd106 	br	10038c <nr_flash_write_buffer+0x18>
  100448:	403ff126 	beq	r8,zero,100410 <nr_flash_write_buffer+0x9c>
  10044c:	001d883a 	mov	r14,zero
  100450:	003fef06 	br	100410 <nr_flash_write_buffer+0x9c>

00100454 <main>:

#define FLASH_BASE_ADD 0x200000

int main()
{
  100454:	defffe04 	addi	sp,sp,-8
  100458:	dc400015 	stw	r17,0(sp)
   nr_flash_erase_sector((unsigned short*)na_cfi_flash_0_base,(unsigned short*)(FLASH_BASE_ADD+0x4000));
  10045c:	04400834 	movhi	r17,32
  100460:	8c400004 	addi	r17,r17,0
  100464:	8809883a 	mov	r4,r17
  100468:	01400834 	movhi	r5,32
  10046c:	29500004 	addi	r5,r5,16384
  100470:	dfc00115 	stw	ra,4(sp)
  100474:	01002200 	call	100220 <nr_flash_erase_sector>
   nr_flash_erase_sector((unsigned short*)na_cfi_flash_0_base,(unsigned short*)(FLASH_BASE_ADD+0x6000));
  100478:	8809883a 	mov	r4,r17
  10047c:	01400834 	movhi	r5,32
  100480:	29580004 	addi	r5,r5,24576
  100484:	01002200 	call	100220 <nr_flash_erase_sector>
   nr_flash_erase_sector((unsigned short*)na_cfi_flash_0_base,(unsigned short*)(FLASH_BASE_ADD+0x10000));
  100488:	8809883a 	mov	r4,r17
  10048c:	01400874 	movhi	r5,33
  100490:	29400004 	addi	r5,r5,0
  100494:	01002200 	call	100220 <nr_flash_erase_sector>
   nr_flash_erase_sector((unsigned short*)na_cfi_flash_0_base,(unsigned short*)(FLASH_BASE_ADD+0x20000));
  100498:	8809883a 	mov	r4,r17
  10049c:	014008b4 	movhi	r5,34
  1004a0:	29400004 	addi	r5,r5,0
  1004a4:	01002200 	call	100220 <nr_flash_erase_sector>
   nr_flash_erase_sector((unsigned short*)na_cfi_flash_0_base,(unsigned short*)(FLASH_BASE_ADD+0x30000));
  1004a8:	8809883a 	mov	r4,r17
  1004ac:	014008f4 	movhi	r5,35
  1004b0:	29400004 	addi	r5,r5,0
  1004b4:	01002200 	call	100220 <nr_flash_erase_sector>
   nr_flash_erase_sector((unsigned short*)na_cfi_flash_0_base,(unsigned short*)(FLASH_BASE_ADD+0x40000));
  1004b8:	8809883a 	mov	r4,r17
  1004bc:	01400934 	movhi	r5,36
  1004c0:	29400004 	addi	r5,r5,0
  1004c4:	01002200 	call	100220 <nr_flash_erase_sector>
   nr_flash_erase_sector((unsigned short*)na_cfi_flash_0_base,(unsigned short*)(FLASH_BASE_ADD+0x50000));
  1004c8:	8809883a 	mov	r4,r17
  1004cc:	01400974 	movhi	r5,37
  1004d0:	29400004 	addi	r5,r5,0
  1004d4:	01002200 	call	100220 <nr_flash_erase_sector>
   nr_flash_erase_sector((unsigned short*)na_cfi_flash_0_base,(unsigned short*)(FLASH_BASE_ADD+0x60000));
  1004d8:	8809883a 	mov	r4,r17
  1004dc:	014009b4 	movhi	r5,38
  1004e0:	29400004 	addi	r5,r5,0
  1004e4:	01002200 	call	100220 <nr_flash_erase_sector>
	
}
  1004e8:	0005883a 	mov	r2,zero
  1004ec:	dfc00117 	ldw	ra,4(sp)
  1004f0:	dc400017 	ldw	r17,0(sp)
  1004f4:	dec00204 	addi	sp,sp,8
  1004f8:	f800283a 	ret

001004fc <call_functions>:
  1004fc:	defffd04 	addi	sp,sp,-12
  100500:	dc000115 	stw	r16,4(sp)
  100504:	dc400015 	stw	r17,0(sp)
  100508:	2c3fff04 	addi	r16,r5,-4
  10050c:	2023883a 	mov	r17,r4
  100510:	dfc00215 	stw	ra,8(sp)
  100514:	84400436 	bltu	r16,r17,100528 <call_functions+0x2c>
  100518:	80800017 	ldw	r2,0(r16)
  10051c:	843fff04 	addi	r16,r16,-4
  100520:	103ee83a 	callr	r2
  100524:	847ffc2e 	bgeu	r16,r17,100518 <call_functions+0x1c>
  100528:	dfc00217 	ldw	ra,8(sp)
  10052c:	dc000117 	ldw	r16,4(sp)
  100530:	dc400017 	ldw	r17,0(sp)
  100534:	dec00304 	addi	sp,sp,12
  100538:	f800283a 	ret

0010053c <alt_main>:
  10053c:	01000434 	movhi	r4,16
  100540:	21017704 	addi	r4,r4,1500
  100544:	00800434 	movhi	r2,16
  100548:	10817704 	addi	r2,r2,1500
  10054c:	1105c83a 	sub	r2,r2,r4
  100550:	deffff04 	addi	sp,sp,-4
  100554:	10bfffc4 	addi	r2,r2,-1
  100558:	00ffffc4 	movi	r3,-1
  10055c:	dfc00015 	stw	ra,0(sp)
  100560:	10c00426 	beq	r2,r3,100574 <alt_main+0x38>
  100564:	20000005 	stb	zero,0(r4)
  100568:	10bfffc4 	addi	r2,r2,-1
  10056c:	21000044 	addi	r4,r4,1
  100570:	10fffc1e 	bne	r2,r3,100564 <alt_main+0x28>
  100574:	01000434 	movhi	r4,16
  100578:	21017404 	addi	r4,r4,1488
  10057c:	01400434 	movhi	r5,16
  100580:	29417404 	addi	r5,r5,1488
  100584:	01004fc0 	call	1004fc <call_functions>
  100588:	d1200617 	ldw	r4,-32744(gp)
  10058c:	d1600517 	ldw	r5,-32748(gp)
  100590:	d1a00417 	ldw	r6,-32752(gp)
  100594:	01004540 	call	100454 <main>
  100598:	01000434 	movhi	r4,16
  10059c:	21017404 	addi	r4,r4,1488
  1005a0:	01400434 	movhi	r5,16
  1005a4:	29417404 	addi	r5,r5,1488
  1005a8:	01004fc0 	call	1004fc <call_functions>
  1005ac:	003fff06 	br	1005ac <alt_main+0x70>

001005b0 <nr_delay>:
  1005b0:	2011883a 	mov	r8,r4

001005b4 <delay_specified_milliseconds>:
  1005b4:	02000034 	movhi	r8,0
  1005b8:	4230d414 	ori	r8,r8,50000

001005bc <delay_one_millisecond>:
  1005bc:	423fff44 	addi	r8,r8,-3
  1005c0:	023ffe16 	blt	zero,r8,1005bc <delay_one_millisecond>
  1005c4:	213fffc4 	addi	r4,r4,-1
  1005c8:	013ffa16 	blt	zero,r4,1005b4 <delay_specified_milliseconds>
  1005cc:	f800283a 	ret