read_me.txt

来自「好东西啊,PCI的IP核.大家快下吧.@可以用来参考.FPGA设计的」· 文本 代码 · 共 6 行

DELAYED_SYNC module:
Module implements synchronization logic for delayed read or write requests.
Flags are synchronized to pass from requesting clock domain to completing clock domain
and back.
It also implements completion expiration counter and max_retry expired request ditching to 
avoid deadlocks.