wb_tb.v

好东西啊,PCI的IP核.大家快下吧.@可以用来参考.FPGA设计的

//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "wb_tb.v"                                            ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - [e-mail]                                   ////
////      - Miha Dolenc                                           ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Miha Dolenc, [e-mail]          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: wb_tb.v,v $
// Revision 1.3  2001/06/12 11:15:10  mihad
// Changed module parameters
//
//

`include "constants.v"
`include "wbw_wbr_fifos.v"

// Common definitions for simulation purposes
`define Tpci 75 // Tp/2 = 7.5ns => Tp = 15ns => Fpci = 66MHz
`define Twb 25  // Tp/2 = 2.5ns =>   Tp = 5ns  => Fwb  = 200MHz

module WB_TB() ;

reg [31:0] wbw_data_in ;
wire [31:0] wbw_data_out;
reg [3:0]  wbw_cbe_in ;
wire [3:0] wbw_cbe_out ;
reg [3:0] wbw_control_in ;
wire [3:0] wbw_control_out ;

wire [31:0] wbr_data_out;
reg [31:0] wbr_data_in;
wire [3:0] wbr_be_out ;
reg [3:0] wbr_be_in ;
reg [3:0] wbr_control_in ;
wire [3:0] wbr_control_out ;

wire wbw_full;
wire wbw_empty ;
wire wbw_almost_full ;
wire wbw_almost_empty ;
reg wbw_wenable ;
reg wbw_renable ;
wire wbw_transaction_ready ;

wire wbr_full;
wire wbr_empty ;
wire wbr_almost_full ;
wire wbr_almost_empty ;
reg wbr_wenable ;
reg wbr_renable ;
wire wbr_transaction_ready ;

reg reset ;
reg pci_clock ;
reg wb_clock ;

reg wbr_flush ;
reg wbw_flush ;

`ifdef FPGA
    assign glbl.GSR = reset ;
`endif

// initial values
initial
begin
    reset <= 1'b1 ;

    pci_clock <= 1'b1 ;
    wb_clock <= 1'b0 ;
    wbw_data_in <= 32'h00000001 ;
    wbw_cbe_in  <= 4'h0 ;
    wbr_be_in  <= 4'h0 ;
    wbw_control_in <= 4'h1 ;
    wbw_wenable <= 1'b0;
    wbw_renable <= 1'b0 ;
    wbr_control_in <= 4'h1 ;
    wbr_wenable <= 1'b0;
    wbr_renable <= 1'b0 ;
    wbr_data_in <= 32'h00000001 ;
    wbr_flush <= 1'b0 ;

    #10 reset = 1'b0 ;
    run_tests ;
end 

// clock generation
always 
begin
   #`Tpci pci_clock = ~pci_clock ;
end

always 
begin
   #`Twb wb_clock = ~wb_clock ;
end

task run_tests;
begin
    wbw_empty_nempty_transition ;
    $display("Empty/not empty transition test for WBW completed") ;
    wbw_full_empty ;
    $display("Full/empty status generation test for WBW completed") ;
    
    wbr_empty_nempty_transition ;
    $display("Empty/not empty transition test for WBR completed") ;
    wbr_full_empty ;
    $display("Full/empty status generation test for WBR completed") ;

    simultaneous_operation ;
    $stop ;
end
endtask

task wbw_empty_nempty_transition ;
    integer index ;
    integer read_data ;
begin
    read_data = 1 ;
    fork
    begin:write_wbw_once
        // repeat the test several times, so clock to clock transition time changes
        for(index = 2; index <= 101; index = index + 1)
        begin
            // wait for WBW to become empty
            wait(wbw_empty);
            // sample empty on posedge of clock
            @(posedge wb_clock)
                wbw_wenable <= #`FF_DELAY 1'b1;
                
            // data gets written at clock edge following the one empty was asserted
            @(posedge wb_clock)
            begin
                // prepare data for next write
                wbw_wenable <= #`FF_DELAY 1'b0 ;
                wbw_data_in <= #`FF_DELAY index ;
                wbw_control_in <= #`FF_DELAY index[3:0] ;
                wbw_cbe_in <= #`FF_DELAY index[7:4] ;
                // wait for WBW to be empty again
                wait(~wbw_empty) ;
            end
        end
    end

    begin:read_wbw
        // repeat test several times
        while(read_data <= 100)
        begin
            wait (~wbw_empty) ;
            @(posedge pci_clock)
                // at first clock edge empty is deasserted assert read enable, so read will be performed on the next clk edge
                wbw_renable <= #`FF_DELAY 1'b1 ;
            @(posedge pci_clock)
            begin
                // sample read data
                if ((wbw_data_out != read_data) || (read_data[3:0] != wbw_control_out) || (read_data[7:4] != wbw_cbe_out))
                begin
                    $display("Empty/not empty transition test failed for WBW fifo! On read number %d !", index) ;
                    $stop ;
                end
                // prepare data for next read sampling
                read_data <= read_data + 32'd1 ;
                wbw_renable <= #`FF_DELAY 1'b0 ;
                @(posedge pci_clock) ;
            end
        end
    end
    join
end
endtask

task wbw_full_empty;
    integer windex ;
    integer rindex ;
begin
    // task fills FIFO until it is full and monitors status outputs if they are asserted correctly
    windex = 1 ;
    wbw_data_in <= #`FF_DELAY 32'h00000001 ;
    wbw_control_in <= #`FF_DELAY 4'h1 ;
    wbw_cbe_in <= #`FF_DELAY 4'h0 ;
    begin:fill_FIFO
        @(posedge wb_clock)
            wbw_wenable <= #`FF_DELAY 1'b1 ;
        while (windex < `WBW_DEPTH)
        begin
            @(posedge wb_clock)
            begin
                windex = windex + 1 ;
                wbw_data_in <= #`FF_DELAY windex ;
                wbw_control_in <= #`FF_DELAY windex[3:0] ;
                wbw_cbe_in <= #`FF_DELAY windex[7:4] ;
                
                if (windex == (`WBW_DEPTH))
                begin
                    if (~wbw_almost_full)
                    begin
                        $display("Almost full status generation test for WBW failed") ;
                        $stop ;
                    end
                end
            end
        end
        
        wbw_wenable <= #`FF_DELAY 1'b0 ;
        @(posedge wb_clock)
        begin
            if (~wbw_full)
            begin
                $display("Full status generation test for WBW failed") ;
                $stop ;
            end
        end
    end
    
    // statements read from FIFO, monitor data output and status outputs on proper clock edge
    begin:empty_FIFO
        rindex = 0 ;
        wait (wbw_full) ;
        @(posedge pci_clock)
            wbw_renable <= #`FF_DELAY 1'b1 ;
        while(rindex < (`WBW_DEPTH - 1))
        begin
            rindex = rindex + 1 ;
            @(posedge pci_clock)
            begin
                if ((wbw_data_out != rindex) || (rindex[3:0] != wbw_control_out) || (rindex[7:4] != wbw_cbe_out))
                begin
                    $display("Full/Empty status generation test failed for WBW fifo!");
                    $stop ;
                end
                if (rindex == `WBW_DEPTH - 1)
                begin
                    if (~wbw_almost_empty)
                    begin
                        $display("Almost empty status generation test for WBW failed") ;
                        $stop ;
                    end
                end
            end
        end

        wbw_renable <= #`FF_DELAY 1'b0 ;
        @(posedge pci_clock)
        begin
            if (~wbw_empty)
            begin
                $display("Empty status generation test for WBW failed") ;
                $stop ;
            end
        end
    end    
end
endtask


task wbr_empty_nempty_transition ;
    integer index ;
    integer read_data ;
begin
    read_data = 1 ;
    fork
    begin:write_wbr_once
        for(index = 2; index <= 101; index = index + 1)
        begin
            wait(wbr_empty);
            @(posedge pci_clock)
                wbr_wenable <= #`FF_DELAY 1'b1;
                
            // data gets written at next rising clock edge
            @(posedge pci_clock)
            begin
                wbr_wenable <= #`FF_DELAY 1'b0 ;
                wbr_data_in <= #`FF_DELAY index ;
                wbr_control_in <= #`FF_DELAY index[3:0] ;
                wbr_be_in <= #`FF_DELAY index[7:4] ;
                wait(~wbr_empty) ;
            end
        end
    end

    begin:read_wbr
        while(read_data <= 100)
        begin
            wait (~wbr_empty) ;
            @(posedge wb_clock)
                wbr_renable <= #`FF_DELAY 1'b1 ;
            @(posedge wb_clock)
            begin
                if ((wbr_data_out != read_data) || (read_data[3:0] != wbr_control_out) || (read_data[7:4] != wbr_be_out))
                begin
                    $display("Empty/not empty transition test failed for WBR fifo! On read number %d !", index) ;
                    $stop ;
                end
                read_data <= read_data + 32'd1 ;
                wbr_renable <= #`FF_DELAY 1'b0 ;
                @(posedge wb_clock) ;
            end
        end
    end
    join
end
endtask

task wbr_full_empty;
    integer windex ;
    integer rindex ;
begin
    windex = 1 ;
    wbr_data_in <= #`FF_DELAY 32'h00000001 ;
    wbr_control_in <= #`FF_DELAY 4'h1 ;
    wbr_be_in <= #`FF_DELAY 4'h0 ;
    begin:fill_FIFO
        @(posedge pci_clock)
            wbr_wenable <= #`FF_DELAY 1'b1 ;
        while (windex < `WBR_DEPTH)
        begin
            @(posedge pci_clock)
            begin
                windex = windex + 1 ;
                wbr_data_in <= #`FF_DELAY windex ;
                wbr_control_in <= #`FF_DELAY windex[3:0] ;
                wbr_be_in <= #`FF_DELAY windex[7:4] ;
                
                if (windex == (`WBR_DEPTH))