pciw_pcir_fifos.v

好东西啊,PCI的IP核.大家快下吧.@可以用来参考.FPGA设计的

                pcir_write_performed <= #`FF_DELAY 1'b0 ;
            else 
                pcir_write_performed <= #`FF_DELAY pcir_wallow ;
        end

        /*-----------------------------------------------------------------------------------------------------------
        Additional register storing actual PCIW read address. It must be applied to port B during turnaround cycle
        -----------------------------------------------------------------------------------------------------------*/
        reg [(PCIW_ADDR_LENGTH - 1):0] pciw_raddr_0 ;

        always@(posedge wb_clock_in or posedge pciw_clear)
        begin
            if (pciw_clear)
                pciw_raddr_0 <= #`FF_DELAY {PCIW_ADDR_LENGTH{1'b0}} ;
            else
                if(pciw_rallow)
                    pciw_raddr_0 <= #`FF_DELAY pciw_raddr ;
        end 
        
        wire [(PCIW_ADDR_LENGTH - 1):0] pciw_raddr_calc = pcir_write_performed ? pciw_raddr_0 : pciw_raddr ;

        /*-----------------------------------------------------------------------------------------------------------
        Additional register storing actual PCIR read address. It must be applied to port A during turnaround cycle
        -----------------------------------------------------------------------------------------------------------*/
        reg [(PCIR_ADDR_LENGTH - 1):0] pcir_raddr_0 ;

        always@(posedge pci_clock_in or posedge pcir_clear)
        begin
            if(pcir_clear)
                pcir_raddr_0 <= #`FF_DELAY {PCIR_ADDR_LENGTH{1'b0}} ;
            else
                if(pcir_rallow)
                    pcir_raddr_0 <= #`FF_DELAY pcir_raddr ;
        end 
    
        wire [(PCIR_ADDR_LENGTH - 1):0] pcir_raddr_calc = pciw_write_performed ? pcir_raddr_0 : pcir_raddr ;
    
        /*-----------------------------------------------------------------------------------------------------------
        Port A and B enables
        -----------------------------------------------------------------------------------------------------------*/
        wire portA_enable = pciw_wallow || pcir_rallow || pcir_empty || pciw_write_performed ;
        wire portB_enable = pcir_wallow || pciw_rallow || pciw_empty || pcir_write_performed ;

        /*-----------------------------------------------------------------------------------------------------------
        Port A address generation for block SelectRam+ in SpartanII or Virtex
        Port A is clocked by PCI clock, DIA is input for pciw_fifo, DOA is output for pcir_fifo. Address is multiplexed
        between two values.
        Address multiplexing:
        pciw_wenable == 1 => ADDRA = pciw_waddr (write pointer of PCIW_FIFO)
        else                ADDRA = pcir_raddr (read pointer of PCIR_FIFO)
        -----------------------------------------------------------------------------------------------------------*/
        wire [7:0] portA_addr = pciw_wallow ? {pciw_addr_prefix, pciw_waddr} : {pcir_addr_prefix, pcir_raddr_calc} ;
    
        /*-----------------------------------------------------------------------------------------------------------
        Port B address generation for block SelectRam+ in SpartanII or Virtex
        Port B is clocked by PCI clock, DIB is input for pcir_fifo, DOB is output for pciw_fifo. Address is multiplexed
        between two values.
        Address multiplexing:
        pcir_wenable == 1 => ADDRB = pcir_waddr (write pointer of PCIR_FIFO)
        else                ADDRB = pciw_raddr (read pointer of PCIW_FIFO)
        -----------------------------------------------------------------------------------------------------------*/
        wire [7:0] portB_addr = pcir_wallow ? {pcir_addr_prefix, pcir_waddr} : {pciw_addr_prefix, pciw_raddr_calc} ;
    
        // Block SelectRAM+ cells instantiation
        RAMB4_S16_S16 dpram16_1 (.ADDRA(portA_addr), .DIA(pciw_addr_data_in[15:0]), 
                                 .ENA(portA_enable), .RSTA(reset_in),
                                 .CLKA(pci_clock_in), .WEA(pciw_wallow), 
                                 .DOA(pcir_data_out[15:0]),
                                 .ADDRB(portB_addr), .DIB(pcir_data_in[15:0]), 
                                 .ENB(portB_enable), .RSTB(reset_in),
                                 .CLKB(wb_clock_in), .WEB(pcir_wallow), 
                                 .DOB(pciw_addr_data_out[15:0])) ;

        RAMB4_S16_S16 dpram16_2 (.ADDRA(portA_addr), .DIA(pciw_addr_data_in[31:16]), 
                                 .ENA(portA_enable), .RSTA(reset_in),
                                 .CLKA(pci_clock_in), .WEA(pciw_wallow), 
                                 .DOA(pcir_data_out[31:16]),
                                 .ADDRB(portB_addr), .DIB(pcir_data_in[31:16]), 
                                 .ENB(portB_enable), .RSTB(reset_in),
                                 .CLKB(wb_clock_in), .WEB(pcir_wallow), 
                                 .DOB(pciw_addr_data_out[31:16])) ;
    
        RAMB4_S16_S16 dpram16_3 (.ADDRA(portA_addr), .DIA({pciw_control_in, 8'h00, pciw_cbe_in}), 
                                 .ENA(portA_enable), .RSTA(reset_in),
                                 .CLKA(pci_clock_in), .WEA(pciw_wallow), 
                                 .DOA(dpram3_portA_output),
                                 .ADDRB(portB_addr), .DIB({pcir_control_in, 8'h00, pcir_be_in}), 
                                 .ENB(portB_enable), .RSTB(reset_in),
                                 .CLKB(wb_clock_in), .WEB(pcir_wallow), 
                                 .DOB(dpram3_portB_output)) ;
    `endif
    
    
    
    

`else
    wire [39:0] pciw_ram_data_out ;
    wire [39:0] pciw_ram_data_in = {pciw_control_in, pciw_cbe_in, pciw_addr_data_in} ;
    wire [39:0] pcir_ram_data_in = {pcir_control_in, pcir_be_in, pcir_data_in} ;
    wire [39:0] pcir_ram_data_out ;
    assign pciw_control_out   = pciw_ram_data_out[39:36] ;
    assign pciw_cbe_out       = pciw_ram_data_out[35:32] ;
    assign pciw_addr_data_out = pciw_ram_data_out [31:0] ;
    
    assign pcir_control_out   = pcir_ram_data_out[39:36] ;
    assign pcir_be_out        = pcir_ram_data_out[35:32] ;
    assign pcir_data_out      = pcir_ram_data_out [31:0] ;
    
    `ifdef SYNCHRONOUS
    /*-----------------------------------------------------------------------------------------------------------
    ASIC memory primitives will be added here in the near future - currently there is only some generic, 
    behavioral dual port ram here 
    -----------------------------------------------------------------------------------------------------------*/

    wire pciw_read_enable = pciw_rallow || pciw_empty ;
    wire pcir_read_enable = pcir_rallow || pcir_empty ;

    DP_SRAM #(PCIW_ADDR_LENGTH, PCIW_DEPTH) pciw_ram (.reset_in(reset_in), .wclock_in(pci_clock_in), .rclock_in(wb_clock_in), .data_in(pciw_ram_data_in), 
                    .raddr_in(pciw_raddr), .waddr_in(pciw_waddr), .data_out(pciw_ram_data_out), .renable_in(pciw_read_enable), .wenable_in(pciw_wallow));
    
    DP_SRAM #(PCIR_ADDR_LENGTH, PCIR_DEPTH) pcir_ram (.reset_in(reset_in), .wclock_in(wb_clock_in), .rclock_in(pci_clock_in), .data_in(pcir_ram_data_in),
                    .raddr_in(pcir_raddr), .waddr_in(pcir_waddr), .data_out(pcir_ram_data_out), .renable_in(pcir_read_enable), .wenable_in(pcir_wallow));
    
    `else //ASYNCHRONOUS RAM
        DP_ASYNC_RAM #(PCIW_ADDR_LENGTH, PCIW_DEPTH) pciw_ram (.reset_in(reset_in), .wclock_in(pci_clock_in), .data_in(pciw_ram_data_in), 
                    .raddr_in(pciw_raddr), .waddr_in(pciw_waddr), .data_out(pciw_ram_data_out), .wenable_in(pciw_wallow));
    
        DP_ASYNC_RAM #(PCIR_ADDR_LENGTH, PCIR_DEPTH) pcir_ram (.reset_in(reset_in), .wclock_in(wb_clock_in), .data_in(pcir_ram_data_in),
                    .raddr_in(pcir_raddr), .waddr_in(pcir_waddr), .data_out(pcir_ram_data_out), .wenable_in(pcir_wallow));
    `endif
`endif

/*-----------------------------------------------------------------------------------------------------------
Instantiation of two control logic modules - one for PCIW_FIFO and one for PCIR_FIFO
-----------------------------------------------------------------------------------------------------------*/
FIFO_CONTROL #(PCIW_ADDR_LENGTH) pciw_fifo_ctrl
              (.rclock_in(wb_clock_in), .wclock_in(pci_clock_in), .renable_in(pciw_renable_in), 
               .wenable_in(pciw_wenable_in), .reset_in(reset_in), .flush_in(pciw_flush_in), 
               .almost_full_out(pciw_almost_full_out), .full_out(pciw_full_out), 
               .almost_empty_out(pciw_almost_empty_out), .empty_out(pciw_empty), 
               .waddr_out(pciw_waddr), .raddr_out(pciw_raddr), 
               .rallow_out(pciw_rallow), .wallow_out(pciw_wallow)); 

FIFO_CONTROL #(PCIR_ADDR_LENGTH) pcir_fifo_ctrl
              (.rclock_in(pci_clock_in), .wclock_in(wb_clock_in), .renable_in(pcir_renable_in), 
               .wenable_in(pcir_wenable_in), .reset_in(reset_in), .flush_in(pcir_flush_in), 
               .almost_full_out(pcir_almost_full_out), .full_out(pcir_full_out), 
               .almost_empty_out(pcir_almost_empty_out), .empty_out(pcir_empty), 
               .waddr_out(pcir_waddr), .raddr_out(pcir_raddr), 
               .rallow_out(pcir_rallow), .wallow_out(pcir_wallow)); 


// in and out transaction counters
always@(posedge pci_clock_in or posedge pciw_clear)
begin
    if (pciw_clear)
        pciw_inTransactionCount <= #`FF_DELAY {PCIW_ADDR_LENGTH{1'b0}} ;
    else
        if (pciw_last_in && pciw_wallow)
            pciw_inTransactionCount <= #`FF_DELAY pciw_inTransactionCount + 1'b1 ;
end

always@(posedge wb_clock_in or posedge pciw_clear)
begin
    if (pciw_clear)
        pciw_outTransactionCount <= #`FF_DELAY {PCIW_ADDR_LENGTH{1'b0}} ;
    else
        if (pciw_last_out)
            pciw_outTransactionCount <= #`FF_DELAY pciw_outTransactionCount + 1'b1 ;
end

always@(posedge wb_clock_in or posedge pcir_clear)
begin
    if (pcir_clear)
        pcir_inTransactionCount <= #`FF_DELAY 1'b0 ;
    else
        if (pcir_last_in && pcir_wallow)
            pcir_inTransactionCount <= #`FF_DELAY ~pcir_inTransactionCount ;
end
        
always@(posedge pci_clock_in or posedge pcir_clear)
begin
    if (pcir_clear)
        pcir_outTransactionCount <= #`FF_DELAY 1'b0 ;
    else
        if (pcir_last_out)
            pcir_outTransactionCount <= #`FF_DELAY ~pcir_outTransactionCount ;
end

assign pciw_transaction_ready_out  = !(pciw_inTransactionCount == pciw_outTransactionCount)   ;
assign pcir_transaction_ready_out  = !(pcir_inTransactionCount == pcir_outTransactionCount) ;

endmodule