pciw_pcir_fifos.v

好东西啊,PCI的IP核.大家快下吧.@可以用来参考.FPGA设计的

wire pciw_wallow ;
wire pciw_rallow ;

/*-----------------------------------------------------------------------------------------------------------
pcir_wallow = PCIR_FIFO write allow wire - writes to FIFO are allowed when FIFO isn't full and write enable is 1
pcir_rallow = PCIR_FIFO read allow wire - reads from FIFO are allowed when FIFO isn't empty and read enable is 1
-----------------------------------------------------------------------------------------------------------*/
wire pcir_wallow ;
wire pcir_rallow ;

/*-----------------------------------------------------------------------------------------------------------
wires for address port conections from PCIW_FIFO control logic to RAM blocks used for PCIW_FIFO
-----------------------------------------------------------------------------------------------------------*/
wire [(PCIW_ADDR_LENGTH - 1):0] pciw_raddr ;
wire [(PCIW_ADDR_LENGTH - 1):0] pciw_waddr ;

/*-----------------------------------------------------------------------------------------------------------
wires for address port conections from PCIR_FIFO control logic to RAM blocks used for PCIR_FIFO
-----------------------------------------------------------------------------------------------------------*/
wire [(PCIR_ADDR_LENGTH - 1):0] pcir_raddr ;
wire [(PCIR_ADDR_LENGTH - 1):0] pcir_waddr ;

/*-----------------------------------------------------------------------------------------------------------
PCIW_FIFO transaction counters: used to count incoming transactions and outgoing transactions. When number of
input transactions is equal to number of output transactions, it means that there isn't any complete transaction
currently present in the FIFO.
-----------------------------------------------------------------------------------------------------------*/
reg [(PCIW_ADDR_LENGTH - 1):0] pciw_inTransactionCount ;
reg [(PCIW_ADDR_LENGTH - 1):0] pciw_outTransactionCount ;

/*-----------------------------------------------------------------------------------------------------------
FlipFlops for indicating if complete delayed read completion is present in the FIFO
-----------------------------------------------------------------------------------------------------------*/
reg pcir_inTransactionCount ;
reg pcir_outTransactionCount ;
/*-----------------------------------------------------------------------------------------------------------
wires monitoring control bus. When control bus on a write transaction has a value of `LAST, it means that
complete transaction is in the FIFO. When control bus on a read transaction has a value of `LAST,
it means that there was one complete transaction taken out of FIFO.
-----------------------------------------------------------------------------------------------------------*/
wire pciw_last_in  = pciw_wallow && (pciw_control_in == `LAST) ;
wire pciw_last_out = pciw_rallow && (pciw_control_out == `LAST) ;

wire pcir_last_in  = pcir_wallow && (pcir_control_in == `LAST) ;
wire pcir_last_out = pcir_rallow && (pcir_control_out == `LAST) ;

wire pciw_empty ;
wire pcir_empty ;

assign pciw_empty_out = pciw_empty ;
assign pcir_empty_out = pcir_empty ;

// clear wires for clearing FFs and registers
wire pciw_clear = reset_in || pciw_flush_in ; // PCIW_FIFO's clear signal
wire pcir_clear = reset_in || pcir_flush_in ; // PCIR_FIFO's clear signal

`ifdef FPGA
/*-----------------------------------------------------------------------------------------------------------
this code is included only for FPGA core usage - somewhat different logic because of sharing
one block selectRAM+ between two FIFOs
-----------------------------------------------------------------------------------------------------------*/
    `ifdef BIG
        /*-----------------------------------------------------------------------------------------------------------
        Big FPGAs
        PCIW_FIFO and PCIR_FIFO address prefixes - used for extending read and write addresses because of varible
        FIFO depth and fixed SelectRAM+ size. Addresses are zero paded on the left to form long enough address
        -----------------------------------------------------------------------------------------------------------*/
        wire [(7 - PCIW_ADDR_LENGTH):0] pciw_addr_prefix = {( 8 - PCIW_ADDR_LENGTH){1'b0}} ;
        wire [(7 - PCIR_ADDR_LENGTH):0] pcir_addr_prefix = {( 8 - PCIR_ADDR_LENGTH){1'b0}} ;

        // compose addresses
        wire [7:0] pciw_whole_waddr = {pciw_addr_prefix, pciw_waddr} ;
        wire [7:0] pciw_whole_raddr = {pciw_addr_prefix, pciw_raddr} ;
        
        wire [7:0] pcir_whole_waddr = {pcir_addr_prefix, pcir_waddr} ;
        wire [7:0] pcir_whole_raddr = {pcir_addr_prefix, pcir_raddr} ;

        /*-----------------------------------------------------------------------------------------------------------
        Only 8 bits out of 16 are used in ram3 and ram6 - wires for referencing them
        -----------------------------------------------------------------------------------------------------------*/
        wire [15:0] dpram3_portB_output ;
        wire [15:0] dpram6_portA_output ;

        /*-----------------------------------------------------------------------------------------------------------
        Control out assignements from ram3 output
        -----------------------------------------------------------------------------------------------------------*/
        assign pciw_control_out = dpram3_portB_output[15:12] ;
        assign pcir_control_out = dpram6_portA_output[15:12] ;

        assign pciw_cbe_out = dpram3_portB_output[3:0] ;
        assign pcir_be_out  = dpram6_portA_output[3:0] ;

        wire pciw_read_enable = pciw_rallow || pciw_empty ;
        wire pcir_read_enable = pcir_rallow || pcir_empty ;
        
        // Block SelectRAM+ cells instantiation
        RAMB4_S16_S16 dpram16_1 (.ADDRA(pciw_whole_waddr), .DIA(pciw_addr_data_in[15:0]), 
                                 .ENA(vcc), .RSTA(reset_in),
                                 .CLKA(pci_clock_in), .WEA(pciw_wallow), 
                                 .DOA(),
                                 .ADDRB(pciw_whole_raddr), .DIB(16'h0000), 
                                 .ENB(pciw_read_enable), .RSTB(reset_in),
                                 .CLKB(wb_clock_in), .WEB(gnd), 
                                 .DOB(pciw_addr_data_out[15:0])) ;

        RAMB4_S16_S16 dpram16_2 (.ADDRA(pciw_whole_waddr), .DIA(pciw_addr_data_in[31:16]), 
                                 .ENA(vcc), .RSTA(reset_in),
                                 .CLKA(pci_clock_in), .WEA(pciw_wallow), 
                                 .DOA(),
                                 .ADDRB(pciw_whole_raddr), .DIB(16'h0000), 
                                 .ENB(pciw_read_enable), .RSTB(reset_in),
                                 .CLKB(wb_clock_in), .WEB(gnd), 
                                 .DOB(pciw_addr_data_out[31:16])) ;
    
        RAMB4_S16_S16 dpram16_3 (.ADDRA(pciw_whole_waddr), .DIA({pciw_control_in, 8'h00, pciw_cbe_in}), 
                                 .ENA(vcc), .RSTA(reset_in),
                                 .CLKA(pci_clock_in), .WEA(pciw_wallow), 
                                 .DOA(),
                                 .ADDRB(pciw_whole_raddr), .DIB(16'h0000), 
                                 .ENB(pciw_read_enable), .RSTB(reset_in),
                                 .CLKB(wb_clock_in), .WEB(gnd), 
                                 .DOB(dpram3_portB_output)) ;

        RAMB4_S16_S16 dpram16_4 (.ADDRA(pcir_whole_raddr), .DIA(16'h0000), 
                                 .ENA(pcir_read_enable), .RSTA(reset_in),
                                 .CLKA(pci_clock_in), .WEA(gnd), 
                                 .DOA(pcir_data_out[15:0]),
                                 .ADDRB(pcir_whole_waddr), .DIB(pcir_data_in[15:0]), 
                                 .ENB(vcc), .RSTB(reset_in),
                                 .CLKB(wb_clock_in), .WEB(pcir_wallow), 
                                 .DOB()) ;

        RAMB4_S16_S16 dpram16_5 (.ADDRA(pcir_whole_raddr), .DIA(16'h0000), 
                                 .ENA(pcir_read_enable), .RSTA(reset_in),
                                 .CLKA(pci_clock_in), .WEA(gnd), 
                                 .DOA(pcir_data_out[31:16]),
                                 .ADDRB(pcir_whole_waddr), .DIB(pcir_data_in[31:16]), 
                                 .ENB(vcc), .RSTB(reset_in),
                                 .CLKB(wb_clock_in), .WEB(pcir_wallow), 
                                 .DOB()) ;
    
        RAMB4_S16_S16 dpram16_6 (.ADDRA(pcir_whole_raddr), .DIA(16'h0000), 
                                 .ENA(pcir_read_enable), .RSTA(reset_in),
                                 .CLKA(pci_clock_in), .WEA(gnd), 
                                 .DOA(dpram6_portA_output),
                                 .ADDRB(pcir_whole_waddr), .DIB({pcir_control_in, 8'h00, pcir_be_in}), 
                                 .ENB(vcc), .RSTB(reset_in),
                                 .CLKB(wb_clock_in), .WEB(pcir_wallow), 
                                 .DOB()) ;

    `else // SMALL FPGAs

        /*-----------------------------------------------------------------------------------------------------------
        Small FPGAs
        PCIW_FIFO and PCIR_FIFO address prefixes - used for extending read and write addresses because of varible
        FIFO depth and fixed SelectRAM+ size. Addresses are always paded, because of RAM sharing between FIFOs
        PCIW addresses are zero padded on the left, PCIR addresses are padded
        with ones on the left
        -----------------------------------------------------------------------------------------------------------*/
        wire [(7 - PCIW_ADDR_LENGTH):0] pciw_addr_prefix = {( 8 - PCIW_ADDR_LENGTH){1'b0}} ;
        wire [(7 - PCIR_ADDR_LENGTH):0] pcir_addr_prefix = {( 8 - PCIR_ADDR_LENGTH){1'b1}} ;

        /*-----------------------------------------------------------------------------------------------------------
        Only 8 bits out of 16 are used in ram3 - wires for referencing them
        -----------------------------------------------------------------------------------------------------------*/
        wire [15:0] dpram3_portA_output ;
        wire [15:0] dpram3_portB_output ;

        /*-----------------------------------------------------------------------------------------------------------
        Control out assignements from ram3 output
        -----------------------------------------------------------------------------------------------------------*/
        assign pciw_control_out = dpram3_portB_output[15:12] ;
        assign pcir_control_out = dpram3_portA_output[15:12] ;

        assign pciw_cbe_out = dpram3_portB_output[3:0] ;
        assign pcir_be_out  = dpram3_portA_output[3:0] ;
        
        /*-----------------------------------------------------------------------------------------------------------
        Logic used for extending port's enable input for one clock cycle to allow address and date change from 
        PCI write fifo's write address and data back to PCI read fifo's address and data ( turnaround cycle )
        -----------------------------------------------------------------------------------------------------------*/
        reg pciw_write_performed ;
        always@(posedge pci_clock_in or posedge reset_in)
        begin
            if (reset_in)
                pciw_write_performed <= #`FF_DELAY 1'b0 ;
            else 
                pciw_write_performed <= #`FF_DELAY pciw_wallow ;
        end

        /*-----------------------------------------------------------------------------------------------------------
        Logic used for extending port's enable input for one clock cycle to allow address and date change from 
        PCI read fifo's write address and data back to PCI write fifo's address and data ( turnaround cycle )
        -----------------------------------------------------------------------------------------------------------*/
        reg pcir_write_performed ;
        always@(posedge wb_clock_in or posedge reset_in)
        begin
            if (reset_in)