test_ddr_command.tdo

来自「一个小测试程序希望,朋友有所帮助,赶快下吧@@!!VERILOG」· TDO 代码 · 共 18 行

## NOTE: Do not edit this file.
## Auto generated by Project Navigator for Verilog Post-PAR Simulation
##
vlib work
## Compile Post-PAR Model for Module ddr_command
vlog  "E:/Xilinx6.1i/verilog/src/glbl.v"
vlog  ddr_command_timesim.v
vlog  test_ddr_command.timesim_tfw
vsim -t 1ps +maxdelays -L simprims_ver  -lib work test_ddr_command glbl
do test_ddr_command.udo
view wave
add wave *
add wave /glbl/GSR
view structure
view signals
run -all
## End