ise_test.npl

来自「一个小测试程序希望,朋友有所帮助,赶快下吧@@!!VERILOG」· NPL 代码 · 共 34 行

JDF G
// Created by Project Navigator ver 1.0
PROJECT ise_test
DESIGN ise_test
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s200
DEVICETIME 1187056968
DEVPKG pq208
DEVPKGTIME 0
DEVSPEED -5
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL Verilog
GENERATEDSIMULATIONMODELTIME 0
SOURCE params.v
SOURCE ddr_command.v
STIMULUS test_ddr_command.tbw
SOURCE ddr_control_interface.v
SOURCE ddr_sdram.v
SOURCE ddr_data_path.v
SOURCE pll1.v
SOURCE altclklock.v
[STATUS-ALL]
ddr_command.ncdFile=WARNINGS,1187062868
ddr_command.ngcFile=WARNINGS,1187060167
[STRATEGY-LIST]
Normal=True