ddr_command.twr

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Release 6.2i Trace G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

E:/Xilinx6.1i/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml ddr_command
ddr_command.ncd -o ddr_command.twr ddr_command.pcf


Design file:              ddr_command.ncd
Physical constraint file: ddr_command.pcf
Device,speed:             xc2s200,-5 (PRODUCTION 1.27 2003-12-13)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock CLK
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
LOAD_MODE   |    6.237(R)|   -1.905(R)|CLK_BUFGP         |   0.000|
PRECHARGE   |    5.608(R)|   -1.909(R)|CLK_BUFGP         |   0.000|
READA       |    7.465(R)|   -2.986(R)|CLK_BUFGP         |   0.000|
REFRESH     |    7.379(R)|   -3.116(R)|CLK_BUFGP         |   0.000|
REF_REQ     |    8.975(R)|   -3.032(R)|CLK_BUFGP         |   0.000|
RESET_N     |    8.572(R)|   -1.701(R)|CLK_BUFGP         |   0.000|
SADDR<0>    |    1.412(R)|   -0.714(R)|CLK_BUFGP         |   0.000|
SADDR<10>   |    4.560(R)|   -3.862(R)|CLK_BUFGP         |   0.000|
SADDR<11>   |    4.702(R)|   -4.004(R)|CLK_BUFGP         |   0.000|
SADDR<12>   |    3.098(R)|   -2.400(R)|CLK_BUFGP         |   0.000|
SADDR<13>   |    2.620(R)|   -1.922(R)|CLK_BUFGP         |   0.000|
SADDR<14>   |    2.671(R)|   -1.973(R)|CLK_BUFGP         |   0.000|
SADDR<15>   |    4.997(R)|   -4.299(R)|CLK_BUFGP         |   0.000|
SADDR<16>   |    2.265(R)|   -1.567(R)|CLK_BUFGP         |   0.000|
SADDR<17>   |    2.307(R)|   -1.609(R)|CLK_BUFGP         |   0.000|
SADDR<18>   |    4.845(R)|   -4.147(R)|CLK_BUFGP         |   0.000|
SADDR<19>   |    2.329(R)|   -0.630(R)|CLK_BUFGP         |   0.000|
SADDR<1>    |    4.346(R)|   -3.648(R)|CLK_BUFGP         |   0.000|
SADDR<20>   |    0.608(R)|    0.090(R)|CLK_BUFGP         |   0.000|
SADDR<21>   |    6.261(R)|   -2.568(R)|CLK_BUFGP         |   0.000|
SADDR<2>    |    4.774(R)|   -4.076(R)|CLK_BUFGP         |   0.000|
SADDR<3>    |    4.929(R)|   -4.231(R)|CLK_BUFGP         |   0.000|
SADDR<4>    |    3.208(R)|   -2.510(R)|CLK_BUFGP         |   0.000|
SADDR<5>    |    2.448(R)|   -1.750(R)|CLK_BUFGP         |   0.000|
SADDR<6>    |    2.676(R)|   -1.978(R)|CLK_BUFGP         |   0.000|
SADDR<7>    |    5.249(R)|   -4.551(R)|CLK_BUFGP         |   0.000|
SADDR<8>    |    1.398(R)|   -0.700(R)|CLK_BUFGP         |   0.000|
SADDR<9>    |    3.594(R)|   -2.896(R)|CLK_BUFGP         |   0.000|
SC_BL<0>    |    4.449(R)|   -1.856(R)|CLK_BUFGP         |   0.000|
SC_BL<1>    |    4.450(R)|   -1.939(R)|CLK_BUFGP         |   0.000|
SC_BL<2>    |    4.145(R)|   -1.457(R)|CLK_BUFGP         |   0.000|
SC_BL<3>    |    4.088(R)|   -1.564(R)|CLK_BUFGP         |   0.000|
SC_PM       |    4.132(R)|   -3.434(R)|CLK_BUFGP         |   0.000|
SC_RC<0>    |    7.266(R)|   -2.223(R)|CLK_BUFGP         |   0.000|
SC_RC<1>    |    7.467(R)|   -2.330(R)|CLK_BUFGP         |   0.000|
WRITEA      |    8.681(R)|   -3.761(R)|CLK_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock CLK to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
BA<0>       |    7.725(R)|CLK_BUFGP         |   0.000|
BA<1>       |    7.722(R)|CLK_BUFGP         |   0.000|
CAS_N       |    7.727(R)|CLK_BUFGP         |   0.000|
CKE         |    7.724(R)|CLK_BUFGP         |   0.000|
CM_ACK      |    7.715(R)|CLK_BUFGP         |   0.000|
CS_N<0>     |    7.772(R)|CLK_BUFGP         |   0.000|
CS_N<1>     |    7.772(R)|CLK_BUFGP         |   0.000|
OE          |    7.770(R)|CLK_BUFGP         |   0.000|
RAS_N       |    7.770(R)|CLK_BUFGP         |   0.000|
REF_ACK     |    7.709(R)|CLK_BUFGP         |   0.000|
SA<0>       |    7.665(R)|CLK_BUFGP         |   0.000|
SA<10>      |    7.720(R)|CLK_BUFGP         |   0.000|
SA<11>      |   11.352(R)|CLK_BUFGP         |   0.000|
SA<1>       |    7.728(R)|CLK_BUFGP         |   0.000|
SA<2>       |    7.724(R)|CLK_BUFGP         |   0.000|
SA<3>       |    7.772(R)|CLK_BUFGP         |   0.000|
SA<4>       |    7.772(R)|CLK_BUFGP         |   0.000|
SA<5>       |    7.725(R)|CLK_BUFGP         |   0.000|
SA<6>       |    7.665(R)|CLK_BUFGP         |   0.000|
SA<7>       |    7.770(R)|CLK_BUFGP         |   0.000|
SA<8>       |    7.770(R)|CLK_BUFGP         |   0.000|
SA<9>       |    7.772(R)|CLK_BUFGP         |   0.000|
WE_N        |    7.715(R)|CLK_BUFGP         |   0.000|
do_load_mode|   12.266(R)|CLK_BUFGP         |   0.000|
do_precharge|   11.994(R)|CLK_BUFGP         |   0.000|
do_reada    |   12.195(R)|CLK_BUFGP         |   0.000|
do_refresh  |   13.094(R)|CLK_BUFGP         |   0.000|
do_writea   |   12.215(R)|CLK_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock CLK
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK            |   10.359|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Tue Aug 14 11:41:15 2007
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Peak Memory Usage: 50 MB