__projnav.log

一个小测试程序希望,朋友有所帮助,赶快下吧@@!!VERILOG

=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK                                | BUFGP                  | 55    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 10.117ns (Maximum Frequency: 98.844MHz)
   Minimum input arrival time before clock: 10.792ns
   Maximum output required time after clock: 10.299ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd f:\ise_test/_ngo -i -p xc2s200-pq208-5
ddr_command.ngc ddr_command.ngd 

Reading NGO file "F:/ise_test/ddr_command.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 39148 kilobytes

Writing NGD file "ddr_command.ngd" ...

Writing NGDBUILD log file "ddr_command.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s200pq208-5".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    1
Logic Utilization:
  Number of Slice Flip Flops:        31 out of  4,704    1%
  Number of 4 input LUTs:            80 out of  4,704    1%
Logic Distribution:
    Number of occupied Slices:                          46 out of  2,352    1%
    Number of Slices containing only related logic:     46 out of     46  100%
    Number of Slices containing unrelated logic:         0 out of     46    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:           81 out of  4,704    1%
      Number used as logic:                        80
      Number used as Shift registers:               1
   Number of bonded IOBs:            65 out of    140   46%
      IOB Flip Flops:                              23
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  1,040
Additional JTAG gate count for IOBs:  3,168
Peak Memory Usage:  64 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "ddr_command_map.mrp" for details.
Completed process "Map".

Mapping Module ddr_command . . .
MAP command line:
map -intstyle ise -p xc2s200-pq208-5 -cm area -pr b -k 4 -c 100 -tx off -o ddr_command_map.ncd ddr_command.ngd ddr_command.pcf
Mapping Module ddr_command: DONE



Started process "Place & Route".





Constraints file: ddr_command.pcf

Loading device database for application Par from file "ddr_command_map.ncd".
   "ddr_command" is an NCD, version 2.38, device xc2s200, package pq208, speed
-5
Loading device for application Par from file 'v200.nph' in environment
E:/Xilinx6.1i.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            65 out of 140    46%
      Number of LOCed External IOBs    0 out of 65      0%

   Number of SLICEs                   46 out of 2352    1%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989843) REAL time: 2 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.8
.
Phase 5.8 (Checksum:9b4663) REAL time: 2 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 2 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 2 secs 

Writing design to file ddr_command.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 406 unrouted;       REAL time: 2 secs 

Phase 2: 357 unrouted;       REAL time: 2 secs 

Phase 3: 93 unrouted;       REAL time: 2 secs 

Phase 4: 0 unrouted;       REAL time: 2 secs 

Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 1 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         CLK_BUFGP          |  Global  |   49   |  0.141     |  0.691      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 3 secs 
Total CPU time to PAR completion: 1 secs 

Peak Memory Usage:  54 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file ddr_command.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Tue Aug 14 11:41:15 2007
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module ddr_command . . .
PAR command line: par -w -intstyle ise -ol std -t 1 ddr_command_map.ncd ddr_command.ncd ddr_command.pcf
PAR completed successfully



Started process "Generate Post-Place & Route Simulation Model".

INFO:NetListWriters:580 - If Verilog simulation is performed outside the ISE
   Project Navigator environment, please add $XILINX/verilog/src/glbl.v to the
   simulator compile and invocation commands in order to allow proper
   initialization of the design. If simulation is performed within Project
   Navigator, this will be taken care of automatically. For more information on
   compiling and performing Xilinx simulation, consult the online Synthesis and
   Simulation Design Guide:
   http://support.xilinx.com/support/software_manuals.htm 
Completed process "Generate Post-Place & Route Simulation Model".


Compiling source file "ddr_command.v"
Compiling include file "F:/ise_test/params.v"



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Generate Post-Translate Simulation Model".

INFO:NetListWriters:580 - If Verilog simulation is performed outside the ISE
   Project Navigator environment, please add $XILINX/verilog/src/glbl.v to the
   simulator compile and invocation commands in order to allow proper
   initialization of the design. If simulation is performed within Project
   Navigator, this will be taken care of automatically. For more information on
   compiling and performing Xilinx simulation, consult the online Synthesis and
   Simulation Design Guide:
   http://support.xilinx.com/support/software_manuals.htm 
Completed process "Generate Post-Translate Simulation Model".


Compiling source file "ddr_command.v"
Compiling include file "F:/ise_test/params.v"