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一个小测试程序希望,朋友有所帮助,赶快下吧@@!!VERILOG

Project Navigator Auto-Make Log File
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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "ddr_command.v"
Compiling include file "D:/Verilog/ipddr/params.v"
Module <ddr_command> compiled
No errors in compilation
Analysis of file <ddr_command.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <ddr_command>.
Module <ddr_command> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================
INFO:Xst:1304 - Contents of register <oe_shift<7>> in unit <ddr_command> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <rw_shift<3>> in unit <ddr_command> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <do_nop> in unit <ddr_command> never changes during circuit operation. The register is replaced by logic.

Synthesizing Unit <ddr_command>.
    Related source file is ddr_command.v.
WARNING:Xst:647 - Input <SC_RRD> is never used.
WARNING:Xst:647 - Input <NOP> is never used.
WARNING:Xst:647 - Input <SC_CL> is never used.
WARNING:Xst:1780 - Signal <do_act> is never used or assigned.
    Register <do_writea1> equivalent to <do_writea> has been removed
    Found 2-bit register for signal <CS_N>.
    Found 2-bit register for signal <BA>.
    Found 1-bit register for signal <WE_N>.
    Found 1-bit register for signal <do_refresh>.
    Found 1-bit register for signal <RAS_N>.
    Found 1-bit register for signal <CM_ACK>.
    Found 1-bit register for signal <do_load_mode>.
    Found 1-bit register for signal <OE>.
    Found 1-bit register for signal <do_precharge>.
    Found 12-bit register for signal <SA>.
    Found 1-bit register for signal <REF_ACK>.
    Found 1-bit register for signal <do_reada>.
    Found 1-bit register for signal <CAS_N>.
    Found 1-bit register for signal <do_writea>.
    Found 1-bit register for signal <CKE>.
    Found 8-bit register for signal <command_delay>.
    Found 1-bit register for signal <command_done>.
    Found 1-bit register for signal <do_rw>.
    Found 1-bit register for signal <oe1>.
    Found 1-bit register for signal <oe2>.
    Found 1-bit register for signal <oe3>.
    Found 1-bit register for signal <oe4>.
    Found 7-bit register for signal <oe_shift<6:0>>.
    Found 1-bit register for signal <rp_done>.
    Found 4-bit register for signal <rp_shift>.
    Found 1-bit register for signal <rw_flag>.
    Found 3-bit register for signal <rw_shift<2:0>>.
    Found 9 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  58 D-type flip-flop(s).
	inferred   9 Multiplexer(s).
Unit <ddr_command> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 55
 1-bit register                    : 54
 2-bit register                    : 1
# Shift Registers                  : 1
 2-bit dynamic shift register      : 1
# Multiplexers                     : 8
 1-bit 2-to-1 multiplexer          : 8

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <rw_shift_2> (without init value) is constant in block <ddr_command>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <oe_shift_4> (without init value) is constant in block <ddr_command>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <oe_shift_5> (without init value) is constant in block <ddr_command>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <oe_shift_6> (without init value) is constant in block <ddr_command>.

Optimizing unit <ddr_command> ...
Loading device for application Xst from file 'v200.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block ddr_command, actual ratio is 1.
FlipFlop do_writea has been replicated 1 time(s)
FlipFlop do_reada has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s200pq208-5 

 Number of Slices:                      48  out of   2352     2%  
 Number of Slice Flip Flops:            54  out of   4704     1%  
 Number of 4 input LUTs:                85  out of   4704     1%  
 Number of bonded IOBs:                 65  out of    144    45%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK                                | BUFGP                  | 55    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 10.817ns (Maximum Frequency: 92.447MHz)
   Minimum input arrival time before clock: 9.839ns
   Maximum output required time after clock: 10.299ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
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Project Navigator Auto-Make Log File
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Project Navigator Auto-Make Log File
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Project Navigator Auto-Make Log File
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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "ddr_command.v"
Compiling include file "F:/ise_test/params.v"
Module <ddr_command> compiled
No errors in compilation
Analysis of file <ddr_command.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <ddr_command>.
Module <ddr_command> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================
INFO:Xst:1304 - Contents of register <do_nop> in unit <ddr_command> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <oe_shift<7>> in unit <ddr_command> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <rw_shift<3>> in unit <ddr_command> never changes during circuit operation. The register is replaced by logic.

Synthesizing Unit <ddr_command>.
    Related source file is ddr_command.v.
WARNING:Xst:647 - Input <SC_RRD> is never used.
WARNING:Xst:647 - Input <NOP> is never used.
WARNING:Xst:647 - Input <SC_CL> is never used.
WARNING:Xst:1780 - Signal <do_act> is never used or assigned.
    Register <do_writea1> equivalent to <do_writea> has been removed
    Found 2-bit register for signal <CS_N>.
    Found 2-bit register for signal <BA>.
    Found 1-bit register for signal <WE_N>.
    Found 1-bit register for signal <do_refresh>.
    Found 1-bit register for signal <RAS_N>.
    Found 1-bit register for signal <CM_ACK>.
    Found 1-bit register for signal <do_load_mode>.
    Found 1-bit register for signal <OE>.
    Found 1-bit register for signal <do_precharge>.
    Found 12-bit register for signal <SA>.
    Found 1-bit register for signal <REF_ACK>.
    Found 1-bit register for signal <do_reada>.
    Found 1-bit register for signal <CAS_N>.
    Found 1-bit register for signal <do_writea>.
    Found 1-bit register for signal <CKE>.
    Found 8-bit register for signal <command_delay>.
    Found 1-bit register for signal <command_done>.
    Found 1-bit register for signal <do_rw>.
    Found 1-bit register for signal <oe1>.
    Found 1-bit register for signal <oe2>.
    Found 1-bit register for signal <oe3>.
    Found 1-bit register for signal <oe4>.
    Found 7-bit register for signal <oe_shift<6:0>>.
    Found 1-bit register for signal <rp_done>.
    Found 4-bit register for signal <rp_shift>.
    Found 1-bit register for signal <rw_flag>.
    Found 3-bit register for signal <rw_shift<2:0>>.
    Found 9 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  58 D-type flip-flop(s).
	inferred   9 Multiplexer(s).
Unit <ddr_command> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 55
 1-bit register                    : 54
 2-bit register                    : 1
# Shift Registers                  : 1
 2-bit dynamic shift register      : 1
# Multiplexers                     : 8
 1-bit 2-to-1 multiplexer          : 8

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <rw_shift_2> (without init value) is constant in block <ddr_command>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <oe_shift_6> (without init value) is constant in block <ddr_command>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <oe_shift_5> (without init value) is constant in block <ddr_command>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <oe_shift_4> (without init value) is constant in block <ddr_command>.

Optimizing unit <ddr_command> ...
Loading device for application Xst from file 'v200.nph' in environment E:/Xilinx6.1i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block ddr_command, actual ratio is 1.
FlipFlop do_writea has been replicated 1 time(s)
FlipFlop do_reada has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s200pq208-5 

 Number of Slices:                      47  out of   2352     1%  
 Number of Slice Flip Flops:            54  out of   4704     1%  
 Number of 4 input LUTs:                84  out of   4704     1%  
 Number of bonded IOBs:                 65  out of    144    45%  
 Number of GCLKs:                        1  out of      4    25%