ddr_command.syr

一个小测试程序希望,朋友有所帮助,赶快下吧@@!!VERILOG

Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: ddr_command.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : ddr_command.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : ddr_command
Output Format                      : NGC
Target Device                      : xc2s200-5-pq208

---- Source Options
Top Module Name                    : ddr_command
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : ddr_command.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "ddr_command.v"
Compiling include file "F:/ise_test/params.v"
Module <ddr_command> compiled
No errors in compilation
Analysis of file <ddr_command.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <ddr_command>.
Module <ddr_command> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================
INFO:Xst:1304 - Contents of register <do_nop> in unit <ddr_command> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <oe_shift<7>> in unit <ddr_command> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <rw_shift<3>> in unit <ddr_command> never changes during circuit operation. The register is replaced by logic.

Synthesizing Unit <ddr_command>.
    Related source file is ddr_command.v.
WARNING:Xst:647 - Input <SC_RRD> is never used.
WARNING:Xst:647 - Input <NOP> is never used.
WARNING:Xst:647 - Input <SC_CL> is never used.
WARNING:Xst:1780 - Signal <do_act> is never used or assigned.
    Register <do_writea1> equivalent to <do_writea> has been removed
    Found 2-bit register for signal <CS_N>.
    Found 2-bit register for signal <BA>.
    Found 1-bit register for signal <WE_N>.
    Found 1-bit register for signal <do_refresh>.
    Found 1-bit register for signal <RAS_N>.
    Found 1-bit register for signal <CM_ACK>.
    Found 1-bit register for signal <do_load_mode>.
    Found 1-bit register for signal <OE>.
    Found 1-bit register for signal <do_precharge>.
    Found 12-bit register for signal <SA>.
    Found 1-bit register for signal <REF_ACK>.
    Found 1-bit register for signal <do_reada>.
    Found 1-bit register for signal <CAS_N>.
    Found 1-bit register for signal <do_writea>.
    Found 1-bit register for signal <CKE>.
    Found 8-bit register for signal <command_delay>.
    Found 1-bit register for signal <command_done>.
    Found 1-bit register for signal <do_rw>.
    Found 1-bit register for signal <oe1>.
    Found 1-bit register for signal <oe2>.
    Found 1-bit register for signal <oe3>.
    Found 1-bit register for signal <oe4>.
    Found 7-bit register for signal <oe_shift<6:0>>.
    Found 1-bit register for signal <rp_done>.
    Found 4-bit register for signal <rp_shift>.
    Found 1-bit register for signal <rw_flag>.
    Found 3-bit register for signal <rw_shift<2:0>>.
    Found 9 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  58 D-type flip-flop(s).
	inferred   9 Multiplexer(s).
Unit <ddr_command> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 55
 1-bit register                    : 54
 2-bit register                    : 1
# Shift Registers                  : 1
 2-bit dynamic shift register      : 1
# Multiplexers                     : 8
 1-bit 2-to-1 multiplexer          : 8

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <rw_shift_2> (without init value) is constant in block <ddr_command>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <oe_shift_6> (without init value) is constant in block <ddr_command>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <oe_shift_5> (without init value) is constant in block <ddr_command>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <oe_shift_4> (without init value) is constant in block <ddr_command>.

Optimizing unit <ddr_command> ...
Loading device for application Xst from file 'v200.nph' in environment E:/Xilinx6.1i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block ddr_command, actual ratio is 1.
FlipFlop do_writea has been replicated 1 time(s)
FlipFlop do_reada has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : ddr_command.ngr
Top Level Output File Name         : ddr_command
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 73

Macro Statistics :
# Registers                        : 55
#      1-bit register              : 54
#      2-bit register              : 1
# Shift Registers                  : 1
#      2-bit dynamic shift register: 1
# Multiplexers                     : 8
#      2-to-1 multiplexer          : 8

Cell Usage :
# BELS                             : 85
#      GND                         : 1
#      LUT1                        : 3
#      LUT2                        : 13
#      LUT2_D                      : 1
#      LUT2_L                      : 9
#      LUT3                        : 11
#      LUT3_L                      : 3
#      LUT4                        : 29
#      LUT4_D                      : 3
#      LUT4_L                      : 11
#      VCC                         : 1
# FlipFlops/Latches                : 54
#      FDC                         : 21
#      FDCE                        : 13
#      FDR                         : 16
#      FDS                         : 4
# Shifters                         : 1
#      SRL16E                      : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 65
#      IBUF                        : 36
#      OBUF                        : 29
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s200pq208-5 

 Number of Slices:                      47  out of   2352     1%  
 Number of Slice Flip Flops:            54  out of   4704     1%  
 Number of 4 input LUTs:                84  out of   4704     1%  
 Number of bonded IOBs:                 65  out of    144    45%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK                                | BUFGP                  | 55    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 10.117ns (Maximum Frequency: 98.844MHz)
   Minimum input arrival time before clock: 10.792ns
   Maximum output required time after clock: 10.299ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'CLK'
Delay:               10.117ns (Levels of Logic = 3)
  Source:            command_done (FF)
  Destination:       do_reada (FF)
  Source Clock:      CLK rising
  Destination Clock: CLK rising

  Data Path: command_done to do_reada
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             16   1.292   2.800  command_done (command_done)
     LUT4_D:I1->O          5   0.653   1.740  _n00621 (_n0062)
     LUT4_L:I0->LO         1   0.653   0.100  Ker24041_SW1 (N3484)
     LUT4:I3->O            2   0.653   1.340  _n01181 (_n0118)
     FDCE:CE                   0.886          do_reada
    ----------------------------------------
    Total                     10.117ns (4.137ns logic, 5.980ns route)
                                       (40.9% logic, 59.1% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK'
Offset:              10.792ns (Levels of Logic = 5)
  Source:            REF_REQ (PAD)
  Destination:       do_reada (FF)
  Destination Clock: CLK rising

  Data Path: REF_REQ to do_reada
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             6   0.924   1.850  REF_REQ_IBUF (REF_REQ_IBUF)
     LUT2:I1->O            2   0.653   1.340  Ker23831_SW0 (N3476)
     LUT4_D:I3->O          5   0.653   1.740  _n00621 (_n0062)
     LUT4_L:I0->LO         1   0.653   0.100  Ker24041_SW1 (N3484)
     LUT4:I3->O            2   0.653   1.340  _n01181 (_n0118)
     FDCE:CE                   0.886          do_reada
    ----------------------------------------
    Total                     10.792ns (4.422ns logic, 6.370ns route)
                                       (41.0% logic, 59.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
Offset:              10.299ns (Levels of Logic = 1)
  Source:            do_writea_1 (FF)
  Destination:       do_writea (PAD)
  Source Clock:      CLK rising

  Data Path: do_writea_1 to do_writea
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q            25   1.292   3.450  do_writea_1 (do_writea_1)
     OBUF:I->O                 5.557          do_writea_OBUF (do_writea)
    ----------------------------------------
    Total                     10.299ns (6.849ns logic, 3.450ns route)
                                       (66.5% logic, 33.5% route)

=========================================================================
CPU : 5.89 / 7.58 s | Elapsed : 6.00 / 7.00 s
 
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Total memory usage is 61044 kilobytes