ddr_command_timesim.v

一个小测试程序希望,朋友有所帮助,赶快下吧@@!!VERILOG

  );
  X_BUF WRITEA_IBUF_50 (
    .I(WRITEA),
    .O(\WRITEA/IBUF )
  );
  X_IPAD \SADDR<13>/PAD  (
    .PAD(SADDR[13])
  );
  X_BUF \SADDR<13>/IMUX  (
    .I(\SADDR<13>/IBUF ),
    .O(SADDR_13_IBUF)
  );
  X_BUF SADDR_13_IBUF_51 (
    .I(SADDR[13]),
    .O(\SADDR<13>/IBUF )
  );
  X_IPAD \SADDR<21>/PAD  (
    .PAD(SADDR[21])
  );
  X_BUF \SADDR<21>/IMUX  (
    .I(\SADDR<21>/IBUF ),
    .O(SADDR_21_IBUF)
  );
  X_BUF SADDR_21_IBUF_52 (
    .I(SADDR[21]),
    .O(\SADDR<21>/IBUF )
  );
  defparam REF_ACK_53.INIT = 1'b0;
  X_FF REF_ACK_53 (
    .I(\REF_ACK/OD ),
    .CE(_n0146),
    .CLK(CLK_BUFGP),
    .SET(GND),
    .RST(\REF_ACK/OFF/RST ),
    .O(REF_ACK_OBUF)
  );
  X_OR2 \REF_ACK/OFF/RSTOR  (
    .I0(\REF_ACK/SRMUXNOT ),
    .I1(GSR),
    .O(\REF_ACK/OFF/RST )
  );
  defparam RAS_N_54.INIT = 1'b1;
  X_SFF RAS_N_54 (
    .I(\RAS_N/OD ),
    .CE(VCC),
    .CLK(CLK_BUFGP),
    .SET(GSR),
    .RST(GND),
    .SSET(\RAS_N/SRMUXNOT ),
    .SRST(GND),
    .O(RAS_N_OBUF)
  );
  X_IPAD \SC_RC<1>/PAD  (
    .PAD(SC_RC[1])
  );
  X_BUF \SC_RC<1>/IMUX  (
    .I(\SC_RC<1>/IBUF ),
    .O(SC_RC_1_IBUF)
  );
  X_BUF SC_RC_1_IBUF_55 (
    .I(SC_RC[1]),
    .O(\SC_RC<1>/IBUF )
  );
  defparam CAS_N_56.INIT = 1'b1;
  X_SFF CAS_N_56 (
    .I(\CAS_N/OD ),
    .CE(VCC),
    .CLK(CLK_BUFGP),
    .SET(GSR),
    .RST(GND),
    .SSET(\CAS_N/SRMUXNOT ),
    .SRST(GND),
    .O(CAS_N_OBUF)
  );
  X_OPAD \CAS_N/PAD  (
    .PAD(CAS_N)
  );
  X_TRI CAS_N_OBUF_57 (
    .I(\CAS_N/OUTMUX ),
    .CTL(\CAS_N/ENABLE ),
    .O(CAS_N)
  );
  X_INV \CAS_N/ENABLEINV  (
    .I(\CAS_N/TORGTS ),
    .O(\CAS_N/ENABLE )
  );
  X_BUF \CAS_N/GTS_OR  (
    .I(GTS),
    .O(\CAS_N/TORGTS )
  );
  X_BUF \CAS_N/OUTMUX_58  (
    .I(CAS_N_OBUF),
    .O(\CAS_N/OUTMUX )
  );
  X_BUF \CAS_N/OMUX  (
    .I(\_n0058/O ),
    .O(\CAS_N/OD )
  );
  X_INV \CAS_N/SRMUX  (
    .I(RESET_N_IBUF),
    .O(\CAS_N/SRMUXNOT )
  );
  X_IPAD \SADDR<14>/PAD  (
    .PAD(SADDR[14])
  );
  X_BUF \SADDR<14>/IMUX  (
    .I(\SADDR<14>/IBUF ),
    .O(SADDR_14_IBUF)
  );
  X_BUF SADDR_14_IBUF_59 (
    .I(SADDR[14]),
    .O(\SADDR<14>/IBUF )
  );
  X_OPAD \OE/PAD  (
    .PAD(OE)
  );
  X_TRI OE_OBUF_60 (
    .I(\OE/OUTMUX ),
    .CTL(\OE/ENABLE ),
    .O(OE)
  );
  X_INV \OE/ENABLEINV  (
    .I(\OE/TORGTS ),
    .O(\OE/ENABLE )
  );
  X_BUF \OE/GTS_OR  (
    .I(GTS),
    .O(\OE/TORGTS )
  );
  X_BUF \OE/OUTMUX_61  (
    .I(OE_OBUF),
    .O(\OE/OUTMUX )
  );
  X_INV \OE/OCEMUX  (
    .I(do_writea_1),
    .O(\OE/OCEMUXNOT )
  );
  X_BUF \OE/OMUX  (
    .I(_n0033),
    .O(\OE/OD )
  );
  X_INV \OE/SRMUX  (
    .I(RESET_N_IBUF),
    .O(\OE/SRMUXNOT )
  );
  X_IPAD \SADDR<15>/PAD  (
    .PAD(SADDR[15])
  );
  X_BUF \SADDR<15>/IMUX  (
    .I(\SADDR<15>/IBUF ),
    .O(SADDR_15_IBUF)
  );
  X_BUF SADDR_15_IBUF_62 (
    .I(SADDR[15]),
    .O(\SADDR<15>/IBUF )
  );
  X_IPAD \SADDR<16>/PAD  (
    .PAD(SADDR[16])
  );
  X_BUF \SADDR<16>/IMUX  (
    .I(\SADDR<16>/IBUF ),
    .O(SADDR_16_IBUF)
  );
  X_BUF SADDR_16_IBUF_63 (
    .I(SADDR[16]),
    .O(\SADDR<16>/IBUF )
  );
  X_IPAD \SADDR<17>/PAD  (
    .PAD(SADDR[17])
  );
  X_BUF \SADDR<17>/IMUX  (
    .I(\SADDR<17>/IBUF ),
    .O(SADDR_17_IBUF)
  );
  X_BUF SADDR_17_IBUF_64 (
    .I(SADDR[17]),
    .O(\SADDR<17>/IBUF )
  );
  X_IPAD \SADDR<18>/PAD  (
    .PAD(SADDR[18])
  );
  X_BUF \SADDR<18>/IMUX  (
    .I(\SADDR<18>/IBUF ),
    .O(SADDR_18_IBUF)
  );
  X_BUF SADDR_18_IBUF_65 (
    .I(SADDR[18]),
    .O(\SADDR<18>/IBUF )
  );
  X_IPAD \LOAD_MODE/PAD  (
    .PAD(LOAD_MODE)
  );
  X_BUF \LOAD_MODE/IMUX  (
    .I(\LOAD_MODE/IBUF ),
    .O(LOAD_MODE_IBUF)
  );
  X_BUF LOAD_MODE_IBUF_66 (
    .I(LOAD_MODE),
    .O(\LOAD_MODE/IBUF )
  );
  X_IPAD \SADDR<19>/PAD  (
    .PAD(SADDR[19])
  );
  X_BUF \SADDR<19>/IMUX  (
    .I(\SADDR<19>/IBUF ),
    .O(SADDR_19_IBUF)
  );
  X_BUF SADDR_19_IBUF_67 (
    .I(SADDR[19]),
    .O(\SADDR<19>/IBUF )
  );
  X_BUF \SADDR<19>/DELAY  (
    .I(\SADDR<19>/IBUF ),
    .O(\SADDR<19>/IDELAY )
  );
  X_OPAD \do_precharge/PAD  (
    .PAD(do_precharge)
  );
  X_TRI do_precharge_OBUF_68 (
    .I(\do_precharge/OUTMUX ),
    .CTL(\do_precharge/ENABLE ),
    .O(do_precharge)
  );
  X_INV \do_precharge/ENABLEINV  (
    .I(\do_precharge/TORGTS ),
    .O(\do_precharge/ENABLE )
  );
  X_BUF \do_precharge/GTS_OR  (
    .I(GTS),
    .O(\do_precharge/TORGTS )
  );
  X_BUF \do_precharge/OUTMUX_69  (
    .I(do_precharge_OBUF),
    .O(\do_precharge/OUTMUX )
  );
  X_OPAD \do_load_mode/PAD  (
    .PAD(do_load_mode)
  );
  X_TRI do_load_mode_OBUF_70 (
    .I(\do_load_mode/OUTMUX ),
    .CTL(\do_load_mode/ENABLE ),
    .O(do_load_mode)
  );
  X_INV \do_load_mode/ENABLEINV  (
    .I(\do_load_mode/TORGTS ),
    .O(\do_load_mode/ENABLE )
  );
  X_BUF \do_load_mode/GTS_OR  (
    .I(GTS),
    .O(\do_load_mode/TORGTS )
  );
  X_BUF \do_load_mode/OUTMUX_71  (
    .I(do_load_mode_OBUF),
    .O(\do_load_mode/OUTMUX )
  );
  X_OPAD \SA<10>/PAD  (
    .PAD(SA[10])
  );
  X_TRI SA_10_OBUF (
    .I(\SA<10>/OUTMUX ),
    .CTL(\SA<10>/ENABLE ),
    .O(SA[10])
  );
  X_INV \SA<10>/ENABLEINV  (
    .I(\SA<10>/TORGTS ),
    .O(\SA<10>/ENABLE )
  );
  X_BUF \SA<10>/GTS_OR  (
    .I(GTS),
    .O(\SA<10>/TORGTS )
  );
  X_BUF \SA<10>/OUTMUX_72  (
    .I(SA_10),
    .O(\SA<10>/OUTMUX )
  );
  X_BUF \SA<10>/OMUX  (
    .I(\_n0044/O ),
    .O(\SA<10>/OD )
  );
  X_INV \SA<10>/SRMUX  (
    .I(RESET_N_IBUF),
    .O(\SA<10>/SRMUXNOT )
  );
  X_IPAD \REF_REQ/PAD  (
    .PAD(REF_REQ)
  );
  X_BUF \REF_REQ/IMUX  (
    .I(\REF_REQ/IBUF ),
    .O(REF_REQ_IBUF)
  );
  X_BUF REF_REQ_IBUF_73 (
    .I(REF_REQ),
    .O(\REF_REQ/IBUF )
  );
  X_OPAD \SA<11>/PAD  (
    .PAD(SA[11])
  );
  X_TRI SA_11_OBUF (
    .I(\SA<11>/OUTMUX ),
    .CTL(\SA<11>/ENABLE ),
    .O(SA[11])
  );
  X_INV \SA<11>/ENABLEINV  (
    .I(\SA<11>/TORGTS ),
    .O(\SA<11>/ENABLE )
  );
  X_BUF \SA<11>/GTS_OR  (
    .I(GTS),
    .O(\SA<11>/TORGTS )
  );
  X_BUF \SA<11>/OUTMUX_74  (
    .I(SA_11),
    .O(\SA<11>/OUTMUX )
  );
  X_OPAD \CS_N<0>/PAD  (
    .PAD(CS_N[0])
  );
  X_TRI CS_N_0_OBUF (
    .I(\CS_N<0>/OUTMUX ),
    .CTL(\CS_N<0>/ENABLE ),
    .O(CS_N[0])
  );
  X_INV \CS_N<0>/ENABLEINV  (
    .I(\CS_N<0>/TORGTS ),
    .O(\CS_N<0>/ENABLE )
  );
  X_BUF \CS_N<0>/GTS_OR  (
    .I(GTS),
    .O(\CS_N<0>/TORGTS )
  );
  X_BUF \CS_N<0>/OUTMUX_75  (
    .I(CS_N_0),
    .O(\CS_N<0>/OUTMUX )
  );
  X_BUF \CS_N<0>/OMUX  (
    .I(_n0056),
    .O(\CS_N<0>/OD )
  );
  X_INV \CS_N<0>/SRMUX  (
    .I(RESET_N_IBUF),
    .O(\CS_N<0>/SRMUXNOT )
  );
  X_ONE \CKE/LOGIC_ONE_76  (
    .O(\CKE/LOGIC_ONE )
  );
  X_OPAD \CKE/PAD  (
    .PAD(CKE)
  );
  X_TRI CKE_OBUF_77 (
    .I(\CKE/OUTMUX ),
    .CTL(\CKE/ENABLE ),
    .O(CKE)
  );
  X_INV \CKE/ENABLEINV  (
    .I(\CKE/TORGTS ),
    .O(\CKE/ENABLE )
  );
  X_BUF \CKE/GTS_OR  (
    .I(GTS),
    .O(\CKE/TORGTS )
  );
  X_BUF \CKE/OUTMUX_78  (
    .I(CKE_OBUF),
    .O(\CKE/OUTMUX )
  );
  X_INV \CKE/SRMUX  (
    .I(RESET_N_IBUF),
    .O(\CKE/SRMUXNOT )
  );
  X_OPAD \do_reada/PAD  (
    .PAD(do_reada)
  );
  X_TRI do_reada_OBUF_79 (
    .I(\do_reada/OUTMUX ),
    .CTL(\do_reada/ENABLE ),
    .O(do_reada)
  );
  X_INV \do_reada/ENABLEINV  (
    .I(\do_reada/TORGTS ),
    .O(\do_reada/ENABLE )
  );
  X_BUF \do_reada/GTS_OR  (
    .I(GTS),
    .O(\do_reada/TORGTS )
  );
  X_BUF \do_reada/OUTMUX_80  (
    .I(do_reada_1),
    .O(\do_reada/OUTMUX )
  );
  X_OPAD \CS_N<1>/PAD  (
    .PAD(CS_N[1])
  );
  X_TRI CS_N_1_OBUF (
    .I(\CS_N<1>/OUTMUX ),
    .CTL(\CS_N<1>/ENABLE ),
    .O(CS_N[1])
  );
  X_INV \CS_N<1>/ENABLEINV  (
    .I(\CS_N<1>/TORGTS ),
    .O(\CS_N<1>/ENABLE )
  );
  X_BUF \CS_N<1>/GTS_OR  (
    .I(GTS),
    .O(\CS_N<1>/TORGTS )
  );
  X_BUF \CS_N<1>/OUTMUX_81  (
    .I(CS_N_1),
    .O(\CS_N<1>/OUTMUX )
  );
  X_INV \CS_N<1>/OMUX  (
    .I(SADDR_21_IBUF),
    .O(\CS_N<1>/ODNOT )
  );
  X_IPAD \SC_RC<0>/PAD  (
    .PAD(SC_RC[0])
  );
  X_BUF \SC_RC<0>/IMUX  (
    .I(\SC_RC<0>/IBUF ),
    .O(SC_RC_0_IBUF)
  );
  X_BUF SC_RC_0_IBUF_82 (
    .I(SC_RC[0]),
    .O(\SC_RC<0>/IBUF )
  );
  defparam Ker24041_SW1.INIT = 16'hF0F4;
  X_LUT4 Ker24041_SW1 (
    .ADR0(command_done),
    .ADR1(PRECHARGE_IBUF),
    .ADR2(_n0062),
    .ADR3(do_precharge_OBUF),
    .O(\Ker24041_SW1/O/FROM )
  );
  defparam _n01181.INIT = 16'h4445;
  X_LUT4 _n01181 (
    .ADR0(_n0090),
    .ADR1(_n0061),
    .ADR2(_n0065),
    .ADR3(\Ker24041_SW1/O ),
    .O(\Ker24041_SW1/O/GROM )
  );
  X_BUF \Ker24041_SW1/O/XUSED  (
    .I(\Ker24041_SW1/O/FROM ),
    .O(\Ker24041_SW1/O )
  );
  X_BUF \Ker24041_SW1/O/YUSED  (
    .I(\Ker24041_SW1/O/GROM ),
    .O(_n0118)
  );
  defparam _n00711.INIT = 16'hFAFA;
  X_LUT4 _n00711 (
    .ADR0(do_writea_1),
    .ADR1(VCC),
    .ADR2(do_reada_1),
    .ADR3(VCC),
    .O(\_n0071/FROM )
  );
  defparam _n00571.INIT = 16'h0001;
  X_LUT4 _n00571 (
    .ADR0(do_refresh_OBUF),
    .ADR1(do_load_mode_OBUF),
    .ADR2(do_precharge_OBUF),
    .ADR3(_n0071),
    .O(\_n0071/GROM )
  );
  X_BUF \_n0071/XUSED  (
    .I(\_n0071/FROM ),
    .O(_n0071)
  );
  X_BUF \_n0071/YUSED  (
    .I(\_n0071/GROM ),
    .O(\_n00571/O )
  );
  defparam SA_0_83.INIT = 1'b0;
  X_SFF SA_0_83 (
    .I(\SA<0>/OD ),
    .CE(VCC),
    .CLK(CLK_BUFGP),
    .SET(GND),
    .RST(GSR),
    .SSET(GND),
    .SRST(\SA<0>/SRMUXNOT ),
    .O(SA_0)
  );
  defparam _n01461_SW0.INIT = 16'hFEFE;
  X_LUT4 _n01461_SW0 (
    .ADR0(do_precharge_OBUF),
    .ADR1(do_reada_1),
    .ADR2(do_writea_OBUF),
    .ADR3(VCC),
    .O(\_n01461_SW0/O/FROM )
  );
  defparam _n01461.INIT = 16'hA0B1;
  X_LUT4 _n01461 (
    .ADR0(do_refresh_OBUF),
    .ADR1(do_load_mode_OBUF),
    .ADR2(REF_REQ_IBUF),
    .ADR3(\_n01461_SW0/O ),
    .O(\_n01461_SW0/O/GROM )
  );
  X_BUF \_n01461_SW0/O/XUSED  (
    .I(\_n01461_SW0/O/FROM ),
    .O(\_n01461_SW0/O )
  );
  X_BUF \_n01461_SW0/O/YUSED  (
    .I(\_n01461_SW0/O/GROM ),
    .O(_n0146)
  );
  defparam _n0033_inst_inv_01.INIT = 16'hDDDD;
  X_LUT4 _n0033_inst_inv_01 (
    .ADR0(SC_RC_1_IBUF),
    .ADR1(SC_RC_0_IBUF),
    .ADR2(VCC),
    .ADR3(VCC),
    .O(\rw_shift<1>/FROM )
  );
  defparam _n00361.INIT = 16'hA088;
  X_LUT4 _n00361 (
    .ADR0(_n0071),
    .ADR1(rw_shift[1]),
    .ADR2(SC_RC_0_IBUF),
    .ADR3(SC_RC_1_IBUF),
    .O(\_n00361/O )
  );
  X_BUF \rw_shift<1>/XUSED  (
    .I(\rw_shift<1>/FROM ),
    .O(_n0033_inst_inv_0)
  );
  X_INV \rw_shift<1>/SRMUX  (
    .I(RESET_N_IBUF),
    .O(\rw_shift<1>/SRMUX_OUTPUTNOT )
  );
  defparam _n012112.INIT = 16'hEFEE;
  X_LUT4 _n012112 (
    .ADR0(CHOICE105),
    .ADR1(do_load_mode_OBUF),
    .ADR2(do_precharge_OBUF),
    .ADR3(PRECHARGE_IBUF),
    .O(\_n012112/O/FROM )
  );
  defparam _n012132.INIT = 16'h0100;
  X_LUT4 _n012132 (
    .ADR0(_n0062),
    .ADR1(_n0090),
    .ADR2(_n0061),
    .ADR3(\_n012112/O ),
    .O(\_n012112/O/GROM )
  );
  X_BUF \_n012112/O/XUSED  (
    .I(\_n012112/O/FROM ),
    .O(\_n012112/O )
  );
  X_BUF \_n012112/O/YUSED  (
    .I(\_n012112/O/GROM ),
    .O(_n0121)
  );
  defparam _n00121.INIT = 16'hFCFC;
  X_LUT4 _n00121 (
    .ADR0(VCC),
    .ADR1(_n0019),
    .ADR2(command_delay[7]),
    .ADR3(VCC),
    .O(\_n00121/O )
  );
  defparam _n00101.INIT = 16'hEEEE;
  X_LUT4 _n00101 (
    .ADR0(command_delay[0]),
    .ADR1(_n0019),
    .ADR2(VCC),
    .ADR3(VCC),
    .O(\_n00101/O )
  );
  X_INV \command_delay<6>/SRMUX  (
    .I(RESET_N_IBUF),
    .O(\command_delay<6>/SRMUX_OUTPUTNOT )
  );
  defparam _n00171.INIT = 16'hEEEE;
  X_LUT4 _n00171 (
    .ADR0(_n0019),
    .ADR1(command_delay[2]),
    .ADR2(VCC),
    .ADR3(VCC),
    .O(\_n00171/O )
  );
  defparam _n00181.INIT = 16'hEEEE;
  X_LUT4 _n00181 (
    .ADR0(_n0019),
    .ADR1(command_delay[1]),
    .ADR2(VCC),
    .ADR3(VCC),
    .O(\_n00181/O )
  );
  X_INV \command_delay<1>/SRMUX  (
    .I(RESET_N_IBUF),
    .O(\command_delay<1>/SRMUX_OUTPUTNOT )
  );
  defparam _n00151.INIT = 16'hFCFC;
  X_LUT4 _n00151 (
    .ADR0(VCC),
    .ADR1(command_delay[4]),
    .ADR2(_n0019),
    .ADR3(VCC),
    .O(\_n00151/O )
  );
  defparam _n00161.INIT = 16'hFFF0;
  X_LUT4 _n00161 (
    .ADR0(VCC),
    .ADR1(VCC),
    .ADR2(_n0019),
    .ADR3(command_delay[3]),
    .O(\_n00161/O )
  );
  X_INV \command_delay<3>/SRMUX  (
    .I(RESET_N_IBUF),
    .O(\command_delay<3>/SRMUX_OUTPUTNOT )
  );
  defparam _n00131.INIT = 16'hFFCC;
  X_LUT4 _n00131 (
    .ADR0(VCC),
    .ADR1(_n0019),
    .ADR2(VCC),
    .ADR3(command_delay[6]),
    .O(\_n00131/O )
  );
  defparam _n00141.INIT = 16'hFFF0;
  X_LUT4 _n00141 (
    .ADR0(VCC),
    .ADR1(VCC),
    .ADR2(command_delay[5]),
    .ADR3(_n0019),
    .O(\_n00141/O )
  );