ddr_command_timesim.v

一个小测试程序希望,朋友有所帮助,赶快下吧@@!!VERILOG

    .I(SADDR[3]),
    .O(\SADDR<3>/IBUF )
  );
  X_IPAD \SC_BL<2>/PAD  (
    .PAD(SC_BL[2])
  );
  X_BUF \SC_BL<2>/IMUX  (
    .I(\SC_BL<2>/IBUF ),
    .O(SC_BL_2_IBUF)
  );
  X_BUF SC_BL_2_IBUF_11 (
    .I(SC_BL[2]),
    .O(\SC_BL<2>/IBUF )
  );
  X_OPAD \WE_N/PAD  (
    .PAD(WE_N)
  );
  X_TRI WE_N_OBUF_12 (
    .I(\WE_N/OUTMUX ),
    .CTL(\WE_N/ENABLE ),
    .O(WE_N)
  );
  X_INV \WE_N/ENABLEINV  (
    .I(\WE_N/TORGTS ),
    .O(\WE_N/ENABLE )
  );
  X_BUF \WE_N/GTS_OR  (
    .I(GTS),
    .O(\WE_N/TORGTS )
  );
  X_BUF \WE_N/OUTMUX_13  (
    .I(WE_N_OBUF),
    .O(\WE_N/OUTMUX )
  );
  X_BUF \WE_N/OMUX  (
    .I(_n0060),
    .O(\WE_N/OD )
  );
  X_IPAD \SADDR<4>/PAD  (
    .PAD(SADDR[4])
  );
  X_BUF \SADDR<4>/IMUX  (
    .I(\SADDR<4>/IBUF ),
    .O(SADDR_4_IBUF)
  );
  X_BUF SADDR_4_IBUF_14 (
    .I(SADDR[4]),
    .O(\SADDR<4>/IBUF )
  );
  X_IPAD \SC_BL<3>/PAD  (
    .PAD(SC_BL[3])
  );
  X_BUF \SC_BL<3>/IMUX  (
    .I(\SC_BL<3>/IBUF ),
    .O(SC_BL_3_IBUF)
  );
  X_BUF SC_BL_3_IBUF_15 (
    .I(SC_BL[3]),
    .O(\SC_BL<3>/IBUF )
  );
  X_IPAD \SADDR<5>/PAD  (
    .PAD(SADDR[5])
  );
  X_BUF \SADDR<5>/IMUX  (
    .I(\SADDR<5>/IBUF ),
    .O(SADDR_5_IBUF)
  );
  X_BUF SADDR_5_IBUF_16 (
    .I(SADDR[5]),
    .O(\SADDR<5>/IBUF )
  );
  X_OPAD \SA<0>/PAD  (
    .PAD(SA[0])
  );
  X_TRI SA_0_OBUF (
    .I(\SA<0>/OUTMUX ),
    .CTL(\SA<0>/ENABLE ),
    .O(SA[0])
  );
  X_INV \SA<0>/ENABLEINV  (
    .I(\SA<0>/TORGTS ),
    .O(\SA<0>/ENABLE )
  );
  X_BUF \SA<0>/GTS_OR  (
    .I(GTS),
    .O(\SA<0>/TORGTS )
  );
  X_BUF \SA<0>/OUTMUX_17  (
    .I(SA_0),
    .O(\SA<0>/OUTMUX )
  );
  X_BUF \SA<0>/OMUX  (
    .I(_n0052),
    .O(\SA<0>/OD )
  );
  X_INV \SA<0>/SRMUX  (
    .I(RESET_N_IBUF),
    .O(\SA<0>/SRMUXNOT )
  );
  X_IPAD \SADDR<6>/PAD  (
    .PAD(SADDR[6])
  );
  X_BUF \SADDR<6>/IMUX  (
    .I(\SADDR<6>/IBUF ),
    .O(SADDR_6_IBUF)
  );
  X_BUF SADDR_6_IBUF_18 (
    .I(SADDR[6]),
    .O(\SADDR<6>/IBUF )
  );
  X_OPAD \SA<1>/PAD  (
    .PAD(SA[1])
  );
  X_TRI SA_1_OBUF (
    .I(\SA<1>/OUTMUX ),
    .CTL(\SA<1>/ENABLE ),
    .O(SA[1])
  );
  X_INV \SA<1>/ENABLEINV  (
    .I(\SA<1>/TORGTS ),
    .O(\SA<1>/ENABLE )
  );
  X_BUF \SA<1>/GTS_OR  (
    .I(GTS),
    .O(\SA<1>/TORGTS )
  );
  X_BUF \SA<1>/OUTMUX_19  (
    .I(SA_1),
    .O(\SA<1>/OUTMUX )
  );
  X_BUF \SA<1>/OMUX  (
    .I(_n0051),
    .O(\SA<1>/OD )
  );
  X_INV \SA<1>/SRMUX  (
    .I(RESET_N_IBUF),
    .O(\SA<1>/SRMUXNOT )
  );
  X_OPAD \do_refresh/PAD  (
    .PAD(do_refresh)
  );
  X_TRI do_refresh_OBUF_20 (
    .I(\do_refresh/OUTMUX ),
    .CTL(\do_refresh/ENABLE ),
    .O(do_refresh)
  );
  X_INV \do_refresh/ENABLEINV  (
    .I(\do_refresh/TORGTS ),
    .O(\do_refresh/ENABLE )
  );
  X_BUF \do_refresh/GTS_OR  (
    .I(GTS),
    .O(\do_refresh/TORGTS )
  );
  X_BUF \do_refresh/OUTMUX_21  (
    .I(do_refresh_OBUF),
    .O(\do_refresh/OUTMUX )
  );
  X_IPAD \SADDR<7>/PAD  (
    .PAD(SADDR[7])
  );
  X_BUF \SADDR<7>/IMUX  (
    .I(\SADDR<7>/IBUF ),
    .O(SADDR_7_IBUF)
  );
  X_BUF SADDR_7_IBUF_22 (
    .I(SADDR[7]),
    .O(\SADDR<7>/IBUF )
  );
  X_OPAD \SA<2>/PAD  (
    .PAD(SA[2])
  );
  X_TRI SA_2_OBUF (
    .I(\SA<2>/OUTMUX ),
    .CTL(\SA<2>/ENABLE ),
    .O(SA[2])
  );
  X_INV \SA<2>/ENABLEINV  (
    .I(\SA<2>/TORGTS ),
    .O(\SA<2>/ENABLE )
  );
  X_BUF \SA<2>/GTS_OR  (
    .I(GTS),
    .O(\SA<2>/TORGTS )
  );
  X_BUF \SA<2>/OUTMUX_23  (
    .I(SA_2),
    .O(\SA<2>/OUTMUX )
  );
  X_BUF \SA<2>/OMUX  (
    .I(_n0050),
    .O(\SA<2>/OD )
  );
  X_INV \SA<2>/SRMUX  (
    .I(RESET_N_IBUF),
    .O(\SA<2>/SRMUXNOT )
  );
  X_OPAD \CM_ACK/PAD  (
    .PAD(CM_ACK)
  );
  X_TRI CM_ACK_OBUF_24 (
    .I(\CM_ACK/OUTMUX ),
    .CTL(\CM_ACK/ENABLE ),
    .O(CM_ACK)
  );
  X_INV \CM_ACK/ENABLEINV  (
    .I(\CM_ACK/TORGTS ),
    .O(\CM_ACK/ENABLE )
  );
  X_BUF \CM_ACK/GTS_OR  (
    .I(GTS),
    .O(\CM_ACK/TORGTS )
  );
  X_BUF \CM_ACK/OUTMUX_25  (
    .I(CM_ACK_OBUF),
    .O(\CM_ACK/OUTMUX )
  );
  X_BUF \CM_ACK/OMUX  (
    .I(_n0019),
    .O(\CM_ACK/OD )
  );
  X_INV \CM_ACK/SRMUX  (
    .I(RESET_N_IBUF),
    .O(\CM_ACK/SRMUXNOT )
  );
  X_IPAD \SADDR<8>/PAD  (
    .PAD(SADDR[8])
  );
  X_BUF \SADDR<8>/IMUX  (
    .I(\SADDR<8>/IBUF ),
    .O(SADDR_8_IBUF)
  );
  X_BUF SADDR_8_IBUF_26 (
    .I(SADDR[8]),
    .O(\SADDR<8>/IBUF )
  );
  X_OPAD \SA<3>/PAD  (
    .PAD(SA[3])
  );
  X_TRI SA_3_OBUF (
    .I(\SA<3>/OUTMUX ),
    .CTL(\SA<3>/ENABLE ),
    .O(SA[3])
  );
  X_INV \SA<3>/ENABLEINV  (
    .I(\SA<3>/TORGTS ),
    .O(\SA<3>/ENABLE )
  );
  X_BUF \SA<3>/GTS_OR  (
    .I(GTS),
    .O(\SA<3>/TORGTS )
  );
  X_BUF \SA<3>/OUTMUX_27  (
    .I(SA_3),
    .O(\SA<3>/OUTMUX )
  );
  X_BUF \SA<3>/OMUX  (
    .I(_n0049),
    .O(\SA<3>/OD )
  );
  X_INV \SA<3>/SRMUX  (
    .I(RESET_N_IBUF),
    .O(\SA<3>/SRMUXNOT )
  );
  X_OPAD \do_writea/PAD  (
    .PAD(do_writea)
  );
  X_TRI do_writea_OBUF_28 (
    .I(\do_writea/OUTMUX ),
    .CTL(\do_writea/ENABLE ),
    .O(do_writea)
  );
  X_INV \do_writea/ENABLEINV  (
    .I(\do_writea/TORGTS ),
    .O(\do_writea/ENABLE )
  );
  X_BUF \do_writea/GTS_OR  (
    .I(GTS),
    .O(\do_writea/TORGTS )
  );
  X_BUF \do_writea/OUTMUX_29  (
    .I(do_writea_1),
    .O(\do_writea/OUTMUX )
  );
  X_IPAD \SADDR<9>/PAD  (
    .PAD(SADDR[9])
  );
  X_BUF \SADDR<9>/IMUX  (
    .I(\SADDR<9>/IBUF ),
    .O(SADDR_9_IBUF)
  );
  X_BUF SADDR_9_IBUF_30 (
    .I(SADDR[9]),
    .O(\SADDR<9>/IBUF )
  );
  X_OPAD \SA<4>/PAD  (
    .PAD(SA[4])
  );
  X_TRI SA_4_OBUF (
    .I(\SA<4>/OUTMUX ),
    .CTL(\SA<4>/ENABLE ),
    .O(SA[4])
  );
  X_INV \SA<4>/ENABLEINV  (
    .I(\SA<4>/TORGTS ),
    .O(\SA<4>/ENABLE )
  );
  X_BUF \SA<4>/GTS_OR  (
    .I(GTS),
    .O(\SA<4>/TORGTS )
  );
  X_BUF \SA<4>/OUTMUX_31  (
    .I(SA_4),
    .O(\SA<4>/OUTMUX )
  );
  X_BUF \SA<4>/OMUX  (
    .I(_n0048),
    .O(\SA<4>/OD )
  );
  X_INV \SA<4>/SRMUX  (
    .I(RESET_N_IBUF),
    .O(\SA<4>/SRMUXNOT )
  );
  X_OPAD \SA<5>/PAD  (
    .PAD(SA[5])
  );
  X_TRI SA_5_OBUF (
    .I(\SA<5>/OUTMUX ),
    .CTL(\SA<5>/ENABLE ),
    .O(SA[5])
  );
  X_INV \SA<5>/ENABLEINV  (
    .I(\SA<5>/TORGTS ),
    .O(\SA<5>/ENABLE )
  );
  X_BUF \SA<5>/GTS_OR  (
    .I(GTS),
    .O(\SA<5>/TORGTS )
  );
  X_BUF \SA<5>/OUTMUX_32  (
    .I(SA_5),
    .O(\SA<5>/OUTMUX )
  );
  X_BUF \SA<5>/OMUX  (
    .I(_n0047),
    .O(\SA<5>/OD )
  );
  X_INV \SA<5>/SRMUX  (
    .I(RESET_N_IBUF),
    .O(\SA<5>/SRMUXNOT )
  );
  X_OPAD \SA<6>/PAD  (
    .PAD(SA[6])
  );
  X_TRI SA_6_OBUF (
    .I(\SA<6>/OUTMUX ),
    .CTL(\SA<6>/ENABLE ),
    .O(SA[6])
  );
  X_INV \SA<6>/ENABLEINV  (
    .I(\SA<6>/TORGTS ),
    .O(\SA<6>/ENABLE )
  );
  X_BUF \SA<6>/GTS_OR  (
    .I(GTS),
    .O(\SA<6>/TORGTS )
  );
  X_BUF \SA<6>/OUTMUX_33  (
    .I(SA_6),
    .O(\SA<6>/OUTMUX )
  );
  X_BUF \SA<6>/OMUX  (
    .I(_n0046),
    .O(\SA<6>/OD )
  );
  X_INV \SA<6>/SRMUX  (
    .I(RESET_N_IBUF),
    .O(\SA<6>/SRMUXNOT )
  );
  X_OPAD \SA<7>/PAD  (
    .PAD(SA[7])
  );
  X_TRI SA_7_OBUF (
    .I(\SA<7>/OUTMUX ),
    .CTL(\SA<7>/ENABLE ),
    .O(SA[7])
  );
  X_INV \SA<7>/ENABLEINV  (
    .I(\SA<7>/TORGTS ),
    .O(\SA<7>/ENABLE )
  );
  X_BUF \SA<7>/GTS_OR  (
    .I(GTS),
    .O(\SA<7>/TORGTS )
  );
  X_BUF \SA<7>/OUTMUX_34  (
    .I(SA_7),
    .O(\SA<7>/OUTMUX )
  );
  X_BUF \SA<7>/OMUX  (
    .I(_n0045),
    .O(\SA<7>/OD )
  );
  X_INV \SA<7>/SRMUX  (
    .I(RESET_N_IBUF),
    .O(\SA<7>/SRMUXNOT )
  );
  X_OPAD \SA<8>/PAD  (
    .PAD(SA[8])
  );
  X_TRI SA_8_OBUF (
    .I(\SA<8>/OUTMUX ),
    .CTL(\SA<8>/ENABLE ),
    .O(SA[8])
  );
  X_INV \SA<8>/ENABLEINV  (
    .I(\SA<8>/TORGTS ),
    .O(\SA<8>/ENABLE )
  );
  X_BUF \SA<8>/GTS_OR  (
    .I(GTS),
    .O(\SA<8>/TORGTS )
  );
  X_BUF \SA<8>/OUTMUX_35  (
    .I(SA_8),
    .O(\SA<8>/OUTMUX )
  );
  X_BUF \SA<8>/OMUX  (
    .I(SADDR_16_IBUF),
    .O(\SA<8>/OD )
  );
  X_OPAD \SA<9>/PAD  (
    .PAD(SA[9])
  );
  X_TRI SA_9_OBUF (
    .I(\SA<9>/OUTMUX ),
    .CTL(\SA<9>/ENABLE ),
    .O(SA[9])
  );
  X_INV \SA<9>/ENABLEINV  (
    .I(\SA<9>/TORGTS ),
    .O(\SA<9>/ENABLE )
  );
  X_BUF \SA<9>/GTS_OR  (
    .I(GTS),
    .O(\SA<9>/TORGTS )
  );
  X_BUF \SA<9>/OUTMUX_36  (
    .I(SA_9),
    .O(\SA<9>/OUTMUX )
  );
  X_BUF \SA<9>/OMUX  (
    .I(SADDR_17_IBUF),
    .O(\SA<9>/OD )
  );
  X_IPAD \RESET_N/PAD  (
    .PAD(RESET_N)
  );
  X_BUF \RESET_N/IMUX  (
    .I(\RESET_N/IBUF ),
    .O(RESET_N_IBUF)
  );
  X_BUF RESET_N_IBUF_37 (
    .I(RESET_N),
    .O(\RESET_N/IBUF )
  );
  X_ZERO \do_nop/LOGIC_ZERO_38  (
    .O(\do_nop/LOGIC_ZERO )
  );
  X_OPAD \do_nop/PAD  (
    .PAD(do_nop)
  );
  X_TRI do_nop_OBUF (
    .I(\do_nop/OUTMUX ),
    .CTL(\do_nop/ENABLE ),
    .O(do_nop)
  );
  X_INV \do_nop/ENABLEINV  (
    .I(\do_nop/TORGTS ),
    .O(\do_nop/ENABLE )
  );
  X_BUF \do_nop/GTS_OR  (
    .I(GTS),
    .O(\do_nop/TORGTS )
  );
  X_BUF \do_nop/OUTMUX_39  (
    .I(\do_nop/LOGIC_ZERO ),
    .O(\do_nop/OUTMUX )
  );
  X_IPAD \REFRESH/PAD  (
    .PAD(REFRESH)
  );
  X_BUF \REFRESH/IMUX  (
    .I(\REFRESH/IBUF ),
    .O(REFRESH_IBUF)
  );
  X_BUF REFRESH_IBUF_40 (
    .I(REFRESH),
    .O(\REFRESH/IBUF )
  );
  defparam WE_N_41.INIT = 1'b1;
  X_SFF WE_N_41 (
    .I(\WE_N/OD ),
    .CE(VCC),
    .CLK(CLK_BUFGP),
    .SET(GSR),
    .RST(GND),
    .SSET(_n0059),
    .SRST(GND),
    .O(WE_N_OBUF)
  );
  X_IPAD \PRECHARGE/PAD  (
    .PAD(PRECHARGE)
  );
  X_BUF \PRECHARGE/IMUX  (
    .I(\PRECHARGE/IBUF ),
    .O(PRECHARGE_IBUF)
  );
  X_BUF PRECHARGE_IBUF_42 (
    .I(PRECHARGE),
    .O(\PRECHARGE/IBUF )
  );
  X_OPAD \BA<0>/PAD  (
    .PAD(BA[0])
  );
  X_TRI BA_0_OBUF (
    .I(\BA<0>/OUTMUX ),
    .CTL(\BA<0>/ENABLE ),
    .O(BA[0])
  );
  X_INV \BA<0>/ENABLEINV  (
    .I(\BA<0>/TORGTS ),
    .O(\BA<0>/ENABLE )
  );
  X_BUF \BA<0>/GTS_OR  (
    .I(GTS),
    .O(\BA<0>/TORGTS )
  );
  X_BUF \BA<0>/OUTMUX_43  (
    .I(BA_0),
    .O(\BA<0>/OUTMUX )
  );
  X_BUF \BA<0>/OMUX  (
    .I(SADDR_19_IBUF),
    .O(\BA<0>/OD )
  );
  X_OPAD \BA<1>/PAD  (
    .PAD(BA[1])
  );
  X_TRI BA_1_OBUF (
    .I(\BA<1>/OUTMUX ),
    .CTL(\BA<1>/ENABLE ),
    .O(BA[1])
  );
  X_INV \BA<1>/ENABLEINV  (
    .I(\BA<1>/TORGTS ),
    .O(\BA<1>/ENABLE )
  );
  X_BUF \BA<1>/GTS_OR  (
    .I(GTS),
    .O(\BA<1>/TORGTS )
  );
  X_BUF \BA<1>/OUTMUX_44  (
    .I(BA_1),
    .O(\BA<1>/OUTMUX )
  );
  X_BUF \BA<1>/OMUX  (
    .I(SADDR_20_IBUF),
    .O(\BA<1>/OD )
  );
  X_IPAD \SC_PM/PAD  (
    .PAD(SC_PM)
  );
  X_BUF \SC_PM/IMUX  (
    .I(\SC_PM/IBUF ),
    .O(SC_PM_IBUF)
  );
  X_BUF SC_PM_IBUF_45 (
    .I(SC_PM),
    .O(\SC_PM/IBUF )
  );
  X_IPAD \SADDR<10>/PAD  (
    .PAD(SADDR[10])
  );
  X_BUF \SADDR<10>/IMUX  (
    .I(\SADDR<10>/IBUF ),
    .O(SADDR_10_IBUF)
  );
  X_BUF SADDR_10_IBUF_46 (
    .I(SADDR[10]),
    .O(\SADDR<10>/IBUF )
  );
  X_IPAD \SADDR<11>/PAD  (
    .PAD(SADDR[11])
  );
  X_BUF \SADDR<11>/IMUX  (
    .I(\SADDR<11>/IBUF ),
    .O(SADDR_11_IBUF)
  );
  X_BUF SADDR_11_IBUF_47 (
    .I(SADDR[11]),
    .O(\SADDR<11>/IBUF )
  );
  X_IPAD \SADDR<12>/PAD  (
    .PAD(SADDR[12])
  );
  X_BUF \SADDR<12>/IMUX  (
    .I(\SADDR<12>/IBUF ),
    .O(SADDR_12_IBUF)
  );
  X_BUF SADDR_12_IBUF_48 (
    .I(SADDR[12]),
    .O(\SADDR<12>/IBUF )
  );
  X_IPAD \SADDR<20>/PAD  (
    .PAD(SADDR[20])
  );
  X_BUF \SADDR<20>/IMUX  (
    .I(\SADDR<20>/IBUF ),
    .O(SADDR_20_IBUF)
  );
  X_BUF SADDR_20_IBUF_49 (
    .I(SADDR[20]),
    .O(\SADDR<20>/IBUF )
  );
  X_IPAD \WRITEA/PAD  (
    .PAD(WRITEA)
  );
  X_BUF \WRITEA/IMUX  (
    .I(\WRITEA/IBUF ),
    .O(WRITEA_IBUF)