ddr_command_timesim.v

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// Xilinx Verilog netlist produced by netgen application (version G.28)
// Command      : -intstyle ise -s 5 -pcf ddr_command.pcf -ngm ddr_command.ngm -w -ofmt verilog -sim ddr_command.ncd ddr_command_timesim.v 
// Input file   : ddr_command.ncd
// Output file  : ddr_command_timesim.v
// Design name  : ddr_command
// # of Modules : 1
// Xilinx       : E:/Xilinx6.1i
// Device       : 2s200pq208-5 (PRODUCTION 1.27 2003-12-13)

// This verilog netlist is a simulation model and uses simulation 
// primitives which may not represent the true implementation of the 
// device, however the netlist is functionally correct and should not 
// be modified. This file cannot be synthesized and should only be used 
// with supported simulation tools.

`timescale 1 ns/1 ps

module ddr_command (
  CKE, do_nop, do_writea, CAS_N, do_reada, REF_ACK, do_precharge, OE, do_load_mode, CM_ACK, RAS_N, do_refresh, WE_N, SC_PM, REF_REQ, READA, NOP, 
WRITEA, PRECHARGE, REFRESH, LOAD_MODE, RESET_N, CLK, SA, BA, CS_N, SC_RC, SADDR, SC_CL, SC_BL, SC_RRD
);
  output CKE;
  output do_nop;
  output do_writea;
  output CAS_N;
  output do_reada;
  output REF_ACK;
  output do_precharge;
  output OE;
  output do_load_mode;
  output CM_ACK;
  output RAS_N;
  output do_refresh;
  output WE_N;
  input SC_PM;
  input REF_REQ;
  input READA;
  input NOP;
  input WRITEA;
  input PRECHARGE;
  input REFRESH;
  input LOAD_MODE;
  input RESET_N;
  input CLK;
  output [11 : 0] SA;
  output [1 : 0] BA;
  output [1 : 0] CS_N;
  input [1 : 0] SC_RC;
  input [21 : 0] SADDR;
  input [1 : 0] SC_CL;
  input [3 : 0] SC_BL;
  input [3 : 0] SC_RRD;
  wire SC_RC_1_IBUF;
  wire CLK_BUFGP;
  wire \_n0058/O ;
  wire RESET_N_IBUF;
  wire READA_IBUF;
  wire _n0146;
  wire _n0040;
  wire \_n00571/O ;
  wire SADDR_0_IBUF;
  wire SADDR_1_IBUF;
  wire SC_BL_0_IBUF;
  wire SADDR_2_IBUF;
  wire SC_BL_1_IBUF;
  wire SADDR_3_IBUF;
  wire SC_BL_2_IBUF;
  wire _n0060;
  wire _n0059;
  wire SADDR_4_IBUF;
  wire SC_BL_3_IBUF;
  wire SADDR_5_IBUF;
  wire _n0052;
  wire SADDR_6_IBUF;
  wire _n0051;
  wire do_refresh_OBUF;
  wire SADDR_7_IBUF;
  wire _n0050;
  wire CM_ACK_N329;
  wire _n0019;
  wire SADDR_8_IBUF;
  wire _n0049;
  wire do_writea_1;
  wire SADDR_9_IBUF;
  wire _n0048;
  wire _n0047;
  wire _n0046;
  wire _n0045;
  wire SADDR_16_IBUF;
  wire _n0116;
  wire SADDR_17_IBUF;
  wire REFRESH_IBUF;
  wire PRECHARGE_IBUF;
  wire SADDR_19_IBUF;
  wire _n0053;
  wire SADDR_20_IBUF;
  wire SC_PM_IBUF;
  wire SADDR_10_IBUF;
  wire SADDR_11_IBUF;
  wire SADDR_12_IBUF;
  wire WRITEA_IBUF;
  wire SADDR_13_IBUF;
  wire SADDR_21_IBUF;
  wire SADDR_14_IBUF;
  wire _n0033;
  wire SADDR_15_IBUF;
  wire SADDR_18_IBUF;
  wire LOAD_MODE_IBUF;
  wire SA_11;
  wire do_precharge_OBUF;
  wire do_load_mode_OBUF;
  wire \_n0044/O ;
  wire REF_REQ_IBUF;
  wire \CLK_BUFGP/IBUFG ;
  wire _n0056;
  wire do_reada_1;
  wire _n0054;
  wire SC_RC_0_IBUF;
  wire _n0062;
  wire command_done;
  wire _n0061;
  wire _n0090;
  wire _n0065;
  wire \Ker24041_SW1/O ;
  wire _n0118;
  wire _n0071;
  wire do_writea_OBUF;
  wire \_n01461_SW0/O ;
  wire _n0033_inst_inv_0;
  wire CHOICE105;
  wire \_n012112/O ;
  wire _n0121;
  wire N2612;
  wire N2372;
  wire N2655;
  wire do_reada_OBUF;
  wire \_n0019_SW0/O ;
  wire do_rw;
  wire \_n0044_SW1/O ;
  wire \_n0119_SW0/O ;
  wire _n0119;
  wire \_n0058_SW0/O ;
  wire _n0120;
  wire rp_done;
  wire \_n0090_SW1/O ;
  wire \Ker24041_SW0/O ;
  wire N3476;
  wire _n0064;
  wire _n0122;
  wire N3488;
  wire _n0145;
  wire _n0034;
  wire oe1;
  wire CHOICE88;
  wire rw_flag;
  wire N3537;
  wire CHOICE98;
  wire oe2;
  wire GLOBAL_LOGIC0;
  wire N2322;
  wire N3529;
  wire N3096;
  wire N3504;
  wire GSR = glbl.GSR;
  wire GTS = glbl.GTS;
  wire \READA/IBUF ;
  wire \REF_ACK/ENABLE ;
  wire \REF_ACK/TORGTS ;
  wire \REF_ACK/OUTMUX ;
  wire REF_ACK_OBUF;
  wire \REF_ACK/OD ;
  wire \REF_ACK/SRMUXNOT ;
  wire \RAS_N/ENABLE ;
  wire \RAS_N/TORGTS ;
  wire \RAS_N/OUTMUX ;
  wire RAS_N_OBUF;
  wire \RAS_N/OD ;
  wire \RAS_N/SRMUXNOT ;
  wire \SADDR<0>/IBUF ;
  wire \SADDR<1>/IBUF ;
  wire \SC_BL<0>/IBUF ;
  wire \SADDR<2>/IBUF ;
  wire \SC_BL<1>/IBUF ;
  wire \SADDR<3>/IBUF ;
  wire \SC_BL<2>/IBUF ;
  wire \WE_N/ENABLE ;
  wire \WE_N/TORGTS ;
  wire \WE_N/OUTMUX ;
  wire WE_N_OBUF;
  wire \WE_N/OD ;
  wire \SADDR<4>/IBUF ;
  wire \SC_BL<3>/IBUF ;
  wire \SADDR<5>/IBUF ;
  wire \SA<0>/ENABLE ;
  wire \SA<0>/TORGTS ;
  wire \SA<0>/OUTMUX ;
  wire SA_0;
  wire \SA<0>/OD ;
  wire \SA<0>/SRMUXNOT ;
  wire \SADDR<6>/IBUF ;
  wire \SA<1>/ENABLE ;
  wire \SA<1>/TORGTS ;
  wire \SA<1>/OUTMUX ;
  wire SA_1;
  wire \SA<1>/OD ;
  wire \SA<1>/SRMUXNOT ;
  wire \do_refresh/ENABLE ;
  wire \do_refresh/TORGTS ;
  wire \do_refresh/OUTMUX ;
  wire \SADDR<7>/IBUF ;
  wire \SA<2>/ENABLE ;
  wire \SA<2>/TORGTS ;
  wire \SA<2>/OUTMUX ;
  wire SA_2;
  wire \SA<2>/OD ;
  wire \SA<2>/SRMUXNOT ;
  wire \CM_ACK/ENABLE ;
  wire \CM_ACK/TORGTS ;
  wire \CM_ACK/OUTMUX ;
  wire CM_ACK_OBUF;
  wire \CM_ACK/OD ;
  wire \CM_ACK/SRMUXNOT ;
  wire \SADDR<8>/IBUF ;
  wire \SA<3>/ENABLE ;
  wire \SA<3>/TORGTS ;
  wire \SA<3>/OUTMUX ;
  wire SA_3;
  wire \SA<3>/OD ;
  wire \SA<3>/SRMUXNOT ;
  wire \do_writea/ENABLE ;
  wire \do_writea/TORGTS ;
  wire \do_writea/OUTMUX ;
  wire \SADDR<9>/IBUF ;
  wire \SA<4>/ENABLE ;
  wire \SA<4>/TORGTS ;
  wire \SA<4>/OUTMUX ;
  wire SA_4;
  wire \SA<4>/OD ;
  wire \SA<4>/SRMUXNOT ;
  wire \SA<5>/ENABLE ;
  wire \SA<5>/TORGTS ;
  wire \SA<5>/OUTMUX ;
  wire SA_5;
  wire \SA<5>/OD ;
  wire \SA<5>/SRMUXNOT ;
  wire \SA<6>/ENABLE ;
  wire \SA<6>/TORGTS ;
  wire \SA<6>/OUTMUX ;
  wire SA_6;
  wire \SA<6>/OD ;
  wire \SA<6>/SRMUXNOT ;
  wire \SA<7>/ENABLE ;
  wire \SA<7>/TORGTS ;
  wire \SA<7>/OUTMUX ;
  wire SA_7;
  wire \SA<7>/OD ;
  wire \SA<7>/SRMUXNOT ;
  wire \SA<8>/ENABLE ;
  wire \SA<8>/TORGTS ;
  wire \SA<8>/OUTMUX ;
  wire SA_8;
  wire \SA<8>/OD ;
  wire \SA<9>/ENABLE ;
  wire \SA<9>/TORGTS ;
  wire \SA<9>/OUTMUX ;
  wire SA_9;
  wire \SA<9>/OD ;
  wire \RESET_N/IBUF ;
  wire \do_nop/ENABLE ;
  wire \do_nop/TORGTS ;
  wire \do_nop/OUTMUX ;
  wire \do_nop/LOGIC_ZERO ;
  wire \REFRESH/IBUF ;
  wire \PRECHARGE/IBUF ;
  wire \BA<0>/ENABLE ;
  wire \BA<0>/TORGTS ;
  wire \BA<0>/OUTMUX ;
  wire BA_0;
  wire \BA<0>/OD ;
  wire \BA<1>/ENABLE ;
  wire \BA<1>/TORGTS ;
  wire \BA<1>/OUTMUX ;
  wire BA_1;
  wire \BA<1>/OD ;
  wire \SC_PM/IBUF ;
  wire \SADDR<10>/IBUF ;
  wire \SADDR<11>/IBUF ;
  wire \SADDR<12>/IBUF ;
  wire \SADDR<20>/IBUF ;
  wire \WRITEA/IBUF ;
  wire \SADDR<13>/IBUF ;
  wire \SADDR<21>/IBUF ;
  wire \REF_ACK/OFF/RST ;
  wire \SC_RC<1>/IBUF ;
  wire \CAS_N/ENABLE ;
  wire \CAS_N/TORGTS ;
  wire \CAS_N/OUTMUX ;
  wire CAS_N_OBUF;
  wire \CAS_N/OD ;
  wire \CAS_N/SRMUXNOT ;
  wire \SADDR<14>/IBUF ;
  wire \OE/ENABLE ;
  wire \OE/TORGTS ;
  wire \OE/OUTMUX ;
  wire OE_OBUF;
  wire \OE/OCEMUXNOT ;
  wire \OE/OD ;
  wire \OE/SRMUXNOT ;
  wire \SADDR<15>/IBUF ;
  wire \SADDR<16>/IBUF ;
  wire \SADDR<17>/IBUF ;
  wire \SADDR<18>/IBUF ;
  wire \LOAD_MODE/IBUF ;
  wire \SADDR<19>/IDELAY ;
  wire \SADDR<19>/IBUF ;
  wire \do_precharge/ENABLE ;
  wire \do_precharge/TORGTS ;
  wire \do_precharge/OUTMUX ;
  wire \do_load_mode/ENABLE ;
  wire \do_load_mode/TORGTS ;
  wire \do_load_mode/OUTMUX ;
  wire \SA<10>/ENABLE ;
  wire \SA<10>/TORGTS ;
  wire \SA<10>/OUTMUX ;
  wire SA_10;
  wire \SA<10>/OD ;
  wire \SA<10>/SRMUXNOT ;
  wire \REF_REQ/IBUF ;
  wire \SA<11>/ENABLE ;
  wire \SA<11>/TORGTS ;
  wire \SA<11>/OUTMUX ;
  wire \CS_N<0>/ENABLE ;
  wire \CS_N<0>/TORGTS ;
  wire \CS_N<0>/OUTMUX ;
  wire CS_N_0;
  wire \CS_N<0>/OD ;
  wire \CS_N<0>/SRMUXNOT ;
  wire \CKE/ENABLE ;
  wire \CKE/TORGTS ;
  wire \CKE/OUTMUX ;
  wire CKE_OBUF;
  wire \CKE/LOGIC_ONE ;
  wire \CKE/SRMUXNOT ;
  wire \do_reada/ENABLE ;
  wire \do_reada/TORGTS ;
  wire \do_reada/OUTMUX ;
  wire \CS_N<1>/ENABLE ;
  wire \CS_N<1>/TORGTS ;
  wire \CS_N<1>/OUTMUX ;
  wire CS_N_1;
  wire \CS_N<1>/ODNOT ;
  wire \SC_RC<0>/IBUF ;
  wire \Ker24041_SW1/O/FROM ;
  wire \Ker24041_SW1/O/GROM ;
  wire \_n0071/FROM ;
  wire \_n0071/GROM ;
  wire \_n01461_SW0/O/FROM ;
  wire \_n01461_SW0/O/GROM ;
  wire \rw_shift<1>/FROM ;
  wire \rw_shift<1>/SRMUX_OUTPUTNOT ;
  wire \_n00361/O ;
  wire \_n012112/O/FROM ;
  wire \_n012112/O/GROM ;
  wire \_n00121/O ;
  wire \command_delay<6>/SRMUX_OUTPUTNOT ;
  wire \_n00101/O ;
  wire \_n00171/O ;
  wire \command_delay<1>/SRMUX_OUTPUTNOT ;
  wire \_n00181/O ;
  wire \_n00151/O ;
  wire \command_delay<3>/SRMUX_OUTPUTNOT ;
  wire \_n00161/O ;
  wire \_n00131/O ;
  wire \command_delay<5>/SRMUX_OUTPUTNOT ;
  wire \_n00141/O ;
  wire \oe_shift<2>/FROM ;
  wire \oe_shift<2>/SRMUX_OUTPUTNOT ;
  wire \_n0029/O ;
  wire \command_delay<7>/FROM ;
  wire \command_delay<7>/SRMUX_OUTPUTNOT ;
  wire \command_delay<7>/GROM ;
  wire \_n0044_SW1/O/FROM ;
  wire \_n0044_SW1/O/GROM ;
  wire \_n0119_SW0/O/FROM ;
  wire \_n0119_SW0/O/GROM ;
  wire \_n0058_SW0/O/FROM ;
  wire \_n0058_SW0/O/GROM ;
  wire \do_refresh_OBUF/FROM ;
  wire \do_refresh_OBUF/SRMUX_OUTPUTNOT ;
  wire \do_refresh_OBUF/GROM ;
  wire \Ker24041_SW0/O/FROM ;
  wire \Ker24041_SW0/O/GROM ;
  wire \do_writea_OBUF/FROM ;
  wire \do_writea_OBUF/GROM ;
  wire \do_writea_OBUF/SRMUX_OUTPUTNOT ;
  wire \do_precharge_OBUF/FROM ;
  wire \do_precharge_OBUF/SRMUX_OUTPUTNOT ;
  wire \do_precharge_OBUF/GROM ;
  wire \rp_done/SRMUX_OUTPUTNOT ;
  wire _n0024;
  wire \do_load_mode_OBUF/FROM ;
  wire \do_load_mode_OBUF/SRMUX_OUTPUTNOT ;
  wire \do_load_mode_OBUF/GROM ;
  wire \do_reada_1/SRMUX_OUTPUTNOT ;
  wire N3546;
  wire _n0022;
  wire \rp_shift<1>/SRMUX_OUTPUTNOT ;
  wire _n0023;
  wire _n0066;
  wire \rp_shift<3>/SRMUX_OUTPUTNOT ;
  wire _n0021;
  wire \do_rw/FROM ;
  wire \do_rw/SRMUX_OUTPUTNOT ;
  wire _n0039;
  wire \oe1/FROM ;
  wire \oe1/SRMUX_OUTPUTNOT ;
  wire _n0032;
  wire \CHOICE88/FROM ;
  wire \CHOICE88/GROM ;
  wire \_n0056/FROM ;
  wire \_n0056/GROM ;
  wire \_n0045/FROM ;
  wire \_n0045/GROM ;
  wire \_n0040/FROM ;
  wire \_n0040/GROM ;
  wire \_n0046/FROM ;
  wire \_n0046/GROM ;
  wire \rw_flag/SRMUX_OUTPUTNOT ;
  wire \N3537/FROM ;
  wire \N3537/GROM ;
  wire \CHOICE98/GROM ;
  wire \_n0048/FROM ;
  wire \_n0048/GROM ;
  wire \do_writea_1/FROM ;
  wire \do_writea_1/SRMUX_OUTPUTNOT ;
  wire N3543;
  wire \CM_ACK_N329/GROM ;
  wire \_n0050/FROM ;
  wire \_n0050/GROM ;
  wire \do_reada_OBUF/FROM ;
  wire \do_reada_OBUF/SRMUX_OUTPUTNOT ;
  wire \do_reada_OBUF/GROM ;
  wire \_n0033/GSHIFT ;
  wire \N2655/GROM ;
  wire \rw_shift<0>/FROM ;
  wire \rw_shift<0>/SRMUX_OUTPUTNOT ;
  wire _n0037;
  wire \oe_shift<3>/FROM ;
  wire \oe_shift<3>/SRMUX_OUTPUTNOT ;
  wire \_n00281/O ;
  wire \oe_shift<0>/FROM ;
  wire \oe_shift<0>/SRMUX_OUTPUTNOT ;
  wire _n0031;
  wire \oe_shift<1>/FROM ;
  wire \oe_shift<1>/SRMUX_OUTPUTNOT ;
  wire _n0030;
  wire \_n0052/GROM ;
  wire \oe2/SRMUX_OUTPUTNOT ;
  wire \oe2/CEMUXNOT ;
  wire \CM_ACK/OFF/RST ;
  wire \rw_shift<1>/FFY/RST ;
  wire \do_precharge_OBUF/FFY/RST ;
  wire \do_writea_OBUF/FFX/RST ;
  wire \rp_done/FFY/RST ;
  wire \do_load_mode_OBUF/FFY/RST ;
  wire \do_reada_1/FFY/RST ;
  wire \rp_shift<1>/FFY/RST ;
  wire \rp_shift<1>/FFX/RST ;
  wire \rp_shift<3>/FFY/RST ;
  wire \do_rw/FFY/RST ;
  wire \OE/OFF/RST ;
  wire \command_delay<6>/FFY/RST ;
  wire \command_delay<1>/FFY/RST ;
  wire \command_delay<6>/FFX/RST ;
  wire \command_delay<1>/FFX/RST ;
  wire \command_delay<3>/FFY/RST ;
  wire \oe_shift<2>/FFY/RST ;
  wire \command_delay<3>/FFX/RST ;
  wire \command_delay<5>/FFY/RST ;
  wire \command_delay<5>/FFX/RST ;
  wire \command_delay<7>/FFY/RST ;
  wire \do_refresh_OBUF/FFY/RST ;
  wire \rp_shift<3>/FFX/RST ;
  wire \oe1/FFY/RST ;
  wire \rw_flag/FFY/RST ;
  wire \do_writea_1/FFY/RST ;
  wire \do_reada_OBUF/FFY/RST ;
  wire \rw_shift<0>/FFY/RST ;
  wire \oe_shift<3>/FFY/RST ;
  wire \oe_shift<0>/FFY/RST ;
  wire \oe_shift<1>/FFY/RST ;
  wire \oe2/FFY/RST ;
  wire \CLK_BUFGP/BUFG/CE ;
  wire \PWR_GND_0/GROM ;
  wire VCC;
  wire GND;
  wire [1 : 0] rw_shift;
  wire [7 : 0] command_delay;
  wire [3 : 0] oe_shift;
  wire [3 : 0] rp_shift;
  initial $sdf_annotate("ddr_command_timesim.sdf");
  X_IPAD \READA/PAD  (
    .PAD(READA)
  );
  X_BUF \READA/IMUX  (
    .I(\READA/IBUF ),
    .O(READA_IBUF)
  );
  X_BUF READA_IBUF_0 (
    .I(READA),
    .O(\READA/IBUF )
  );
  X_OPAD \REF_ACK/PAD  (
    .PAD(REF_ACK)
  );
  X_TRI REF_ACK_OBUF_1 (
    .I(\REF_ACK/OUTMUX ),
    .CTL(\REF_ACK/ENABLE ),
    .O(REF_ACK)
  );
  X_INV \REF_ACK/ENABLEINV  (
    .I(\REF_ACK/TORGTS ),
    .O(\REF_ACK/ENABLE )
  );
  X_BUF \REF_ACK/GTS_OR  (
    .I(GTS),
    .O(\REF_ACK/TORGTS )
  );
  X_BUF \REF_ACK/OUTMUX_2  (
    .I(REF_ACK_OBUF),
    .O(\REF_ACK/OUTMUX )
  );
  X_BUF \REF_ACK/OMUX  (
    .I(_n0040),
    .O(\REF_ACK/OD )
  );
  X_INV \REF_ACK/SRMUX  (
    .I(RESET_N_IBUF),
    .O(\REF_ACK/SRMUXNOT )
  );
  X_OPAD \RAS_N/PAD  (
    .PAD(RAS_N)
  );
  X_TRI RAS_N_OBUF_3 (
    .I(\RAS_N/OUTMUX ),
    .CTL(\RAS_N/ENABLE ),
    .O(RAS_N)
  );
  X_INV \RAS_N/ENABLEINV  (
    .I(\RAS_N/TORGTS ),
    .O(\RAS_N/ENABLE )
  );
  X_BUF \RAS_N/GTS_OR  (
    .I(GTS),
    .O(\RAS_N/TORGTS )
  );
  X_BUF \RAS_N/OUTMUX_4  (
    .I(RAS_N_OBUF),
    .O(\RAS_N/OUTMUX )
  );
  X_BUF \RAS_N/OMUX  (
    .I(\_n00571/O ),
    .O(\RAS_N/OD )
  );
  X_INV \RAS_N/SRMUX  (
    .I(RESET_N_IBUF),
    .O(\RAS_N/SRMUXNOT )
  );
  X_IPAD \SADDR<0>/PAD  (
    .PAD(SADDR[0])
  );
  X_BUF \SADDR<0>/IMUX  (
    .I(\SADDR<0>/IBUF ),
    .O(SADDR_0_IBUF)
  );
  X_BUF SADDR_0_IBUF_5 (
    .I(SADDR[0]),
    .O(\SADDR<0>/IBUF )
  );
  X_IPAD \SADDR<1>/PAD  (
    .PAD(SADDR[1])
  );
  X_BUF \SADDR<1>/IMUX  (
    .I(\SADDR<1>/IBUF ),
    .O(SADDR_1_IBUF)
  );
  X_BUF SADDR_1_IBUF_6 (
    .I(SADDR[1]),
    .O(\SADDR<1>/IBUF )
  );
  X_IPAD \SC_BL<0>/PAD  (
    .PAD(SC_BL[0])
  );
  X_BUF \SC_BL<0>/IMUX  (
    .I(\SC_BL<0>/IBUF ),
    .O(SC_BL_0_IBUF)
  );
  X_BUF SC_BL_0_IBUF_7 (
    .I(SC_BL[0]),
    .O(\SC_BL<0>/IBUF )
  );
  X_IPAD \SADDR<2>/PAD  (
    .PAD(SADDR[2])
  );
  X_BUF \SADDR<2>/IMUX  (
    .I(\SADDR<2>/IBUF ),
    .O(SADDR_2_IBUF)
  );
  X_BUF SADDR_2_IBUF_8 (
    .I(SADDR[2]),
    .O(\SADDR<2>/IBUF )
  );
  X_IPAD \SC_BL<1>/PAD  (
    .PAD(SC_BL[1])
  );
  X_BUF \SC_BL<1>/IMUX  (
    .I(\SC_BL<1>/IBUF ),
    .O(SC_BL_1_IBUF)
  );
  X_BUF SC_BL_1_IBUF_9 (
    .I(SC_BL[1]),
    .O(\SC_BL<1>/IBUF )
  );
  X_IPAD \SADDR<3>/PAD  (
    .PAD(SADDR[3])
  );
  X_BUF \SADDR<3>/IMUX  (
    .I(\SADDR<3>/IBUF ),
    .O(SADDR_3_IBUF)
  );
  X_BUF SADDR_3_IBUF_10 (