ddr_command_translate.v

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// Xilinx Verilog netlist produced by netgen application (version G.28)
// Command      : -intstyle ise -w -ofmt verilog -sim ddr_command.ngd ddr_command_translate.v 
// Input file   : ddr_command.ngd
// Output file  : ddr_command_translate.v
// Design name  : ddr_command
// # of Modules : 1
// Xilinx       : E:/Xilinx6.1i
// Device       : 2s200pq208-5

// This verilog netlist is a simulation model and uses simulation 
// primitives which may not represent the true implementation of the 
// device, however the netlist is functionally correct and should not 
// be modified. This file cannot be synthesized and should only be used 
// with supported simulation tools.

`timescale 1 ns/1 ps

module ddr_command (
  CLK, RESET_N, LOAD_MODE, REFRESH, PRECHARGE, WRITEA, NOP, READA, REF_REQ, SC_PM, WE_N, do_refresh, RAS_N, CM_ACK, do_load_mode, OE, do_precharge, 
REF_ACK, do_reada, CAS_N, do_writea, do_nop, CKE, SC_RRD, SC_BL, SC_CL, SADDR, SC_RC, CS_N, BA, SA
);
  input CLK;
  input RESET_N;
  input LOAD_MODE;
  input REFRESH;
  input PRECHARGE;
  input WRITEA;
  input NOP;
  input READA;
  input REF_REQ;
  input SC_PM;
  output WE_N;
  output do_refresh;
  output RAS_N;
  output CM_ACK;
  output do_load_mode;
  output OE;
  output do_precharge;
  output REF_ACK;
  output do_reada;
  output CAS_N;
  output do_writea;
  output do_nop;
  output CKE;
  input [3 : 0] SC_RRD;
  input [3 : 0] SC_BL;
  input [1 : 0] SC_CL;
  input [21 : 0] SADDR;
  input [1 : 0] SC_RC;
  output [1 : 0] CS_N;
  output [1 : 0] BA;
  output [11 : 0] SA;
  wire SADDR_5_IBUF;
  wire CLK_BUFGP;
  wire RESET_N_IBUF;
  wire LOAD_MODE_IBUF;
  wire REFRESH_IBUF;
  wire WE_N_OBUF;
  wire PRECHARGE_IBUF;
  wire do_refresh_OBUF;
  wire RAS_N_OBUF;
  wire CM_ACK_OBUF;
  wire do_load_mode_OBUF;
  wire OE_OBUF;
  wire do_precharge_OBUF;
  wire SA_9;
  wire SADDR_4_IBUF;
  wire WRITEA_IBUF;
  wire CS_N_1;
  wire REF_ACK_OBUF;
  wire CS_N_0;
  wire do_reada_OBUF;
  wire SA_10;
  wire CAS_N_OBUF;
  wire do_writea_OBUF;
  wire READA_IBUF;
  wire REF_REQ_IBUF;
  wire SADDR_20_IBUF;
  wire SC_PM_IBUF;
  wire SA_11;
  wire do_nop_OBUF;
  wire CKE_OBUF;
  wire SA_8;
  wire do_rw;
  wire oe1;
  wire oe2;
  wire SADDR_12_IBUF;
  wire SA_1;
  wire rp_done;
  wire command_done;
  wire rw_flag;
  wire SADDR_21_IBUF;
  wire SADDR_17_IBUF;
  wire SADDR_1_IBUF;
  wire BA_1;
  wire _n0010;
  wire SA_6;
  wire SADDR_13_IBUF;
  wire _n0012;
  wire _n0013;
  wire SADDR_18_IBUF;
  wire _n0014;
  wire _n0015;
  wire SC_RC_1_IBUF;
  wire _n0016;
  wire _n0021;
  wire _n0017;
  wire _n0022;
  wire _n0018;
  wire _n0023;
  wire _n0019;
  wire _n0024;
  wire SADDR_16_IBUF;
  wire _n0030;
  wire SA_4;
  wire _n0031;
  wire SADDR_7_IBUF;
  wire _n0032;
  wire _n0028;
  wire _n0033;
  wire _n0029;
  wire _n0034;
  wire CM_ACK_N329;
  wire _n0040;
  wire _n0036;
  wire _n0037;
  wire SADDR_14_IBUF;
  wire _n0039;
  wire _n0044;
  wire _n0045;
  wire _n0050;
  wire SA_7;
  wire _n0046;
  wire _n0051;
  wire BA_0;
  wire _n0047;
  wire _n0052;
  wire _n0163;
  wire _n0048;
  wire _n0053;
  wire SA_0;
  wire _n0049;
  wire _n0054;
  wire SC_RC_0_IBUF;
  wire _n0060;
  wire N2372;
  wire SC_BL_3_IBUF;
  wire _n0056;
  wire _n0061;
  wire _n0033_inst_inv_0;
  wire SC_BL_1_IBUF;
  wire _n0057;
  wire _n0062;
  wire SADDR_2_IBUF;
  wire _n0058;
  wire SADDR_11_IBUF;
  wire SC_BL_2_IBUF;
  wire SADDR_6_IBUF;
  wire _n0059;
  wire _n0064;
  wire _n0146;
  wire SC_BL_0_IBUF;
  wire _n0065;
  wire _n0120;
  wire _n0066;
  wire _n0071;
  wire _n0116;
  wire _n0121;
  wire N3488;
  wire SADDR_9_IBUF;
  wire _n0122;
  wire N312;
  wire _n0118;
  wire N3480;
  wire _n0090;
  wire _n0119;
  wire SA_5;
  wire SADDR_19_IBUF;
  wire CS_N_0_N342;
  wire SADDR_8_IBUF;
  wire N3484;
  wire OE_N329;
  wire SADDR_10_IBUF;
  wire _n0145;
  wire SA_2;
  wire SADDR_15_IBUF;
  wire SADDR_0_IBUF;
  wire SADDR_3_IBUF;
  wire SA_3;
  wire N2322;
  wire N2612;
  wire N3537;
  wire N3499;
  wire N2910;
  wire N3525;
  wire N2987;
  wire N2655;
  wire N3529;
  wire N3044;
  wire N3096;
  wire N3504;
  wire CHOICE109;
  wire CHOICE105;
  wire N3533;
  wire CHOICE98;
  wire CHOICE88;
  wire N3476;
  wire N3543;
  wire do_writea_1;
  wire N3546;
  wire do_reada_1;
  wire N3553;
  wire N3555;
  wire N3558;
  wire N3572;
  wire \_n0058_SW0/O ;
  wire \_n012112/O ;
  wire \_n0090_SW1/O ;
  wire \Ker24041_SW0/O ;
  wire \_n0058/O ;
  wire \_n00101/O ;
  wire \_n00121/O ;
  wire \_n00131/O ;
  wire \_n00141/O ;
  wire \_n00151/O ;
  wire \_n00161/O ;
  wire \_n00171/O ;
  wire \_n00181/O ;
  wire \_n0019_SW0/O ;
  wire \_n00281/O ;
  wire \Ker24041_SW1/O ;
  wire \_n00361/O ;
  wire \_n00571/O ;
  wire \_n01461_SW0/O ;
  wire \_n0044/O ;
  wire \_n0044_SW1/O ;
  wire \_n0119_SW0/O ;
  wire \_n0029/O ;
  wire \CLK_BUFGP/IBUFG ;
  wire GSR = glbl.GSR;
  wire \command_delay_2.GSR.OR ;
  wire \rp_done.GSR.OR ;
  wire \command_delay_5.GSR.OR ;
  wire \command_delay_4.GSR.OR ;
  wire \command_delay_3.GSR.OR ;
  wire \rp_shift_0.GSR.OR ;
  wire \rp_shift_1.GSR.OR ;
  wire \do_precharge.GSR.OR ;
  wire \rp_shift_2.GSR.OR ;
  wire \rp_shift_3.GSR.OR ;
  wire \do_writea.GSR.OR ;
  wire \do_refresh.GSR.OR ;
  wire \rw_flag.GSR.OR ;
  wire \do_reada.GSR.OR ;
  wire \REF_ACK.GSR.OR ;
  wire \command_delay_1.GSR.OR ;
  wire \command_delay_0.GSR.OR ;
  wire \command_delay_6.GSR.OR ;
  wire \command_done.GSR.OR ;
  wire \command_delay_7.GSR.OR ;
  wire \do_load_mode.GSR.OR ;
  wire \oe_shift_0.GSR.OR ;
  wire \CM_ACK.GSR.OR ;
  wire \oe1.GSR.OR ;
  wire \oe_shift_2.GSR.OR ;
  wire \oe_shift_3.GSR.OR ;
  wire \do_rw.GSR.OR ;
  wire \rw_shift_0.GSR.OR ;
  wire \rw_shift_1.GSR.OR ;
  wire \oe_shift_1.GSR.OR ;
  wire \oe2.GSR.OR ;
  wire \OE.GSR.OR ;
  wire \do_writea_1.GSR.OR ;
  wire \do_reada_1.GSR.OR ;
  wire \WE_N_OBUF.GTS.TRI ;
  wire GTS = glbl.GTS;
  wire \do_refresh_OBUF.GTS.TRI ;
  wire \RAS_N_OBUF.GTS.TRI ;
  wire \CM_ACK_OBUF.GTS.TRI ;
  wire \do_load_mode_OBUF.GTS.TRI ;
  wire \OE_OBUF.GTS.TRI ;
  wire \do_precharge_OBUF.GTS.TRI ;
  wire \REF_ACK_OBUF.GTS.TRI ;
  wire \do_reada_OBUF.GTS.TRI ;
  wire \CAS_N_OBUF.GTS.TRI ;
  wire \do_writea_OBUF.GTS.TRI ;
  wire \do_nop_OBUF.GTS.TRI ;
  wire \CKE_OBUF.GTS.TRI ;
  wire \CS_N_1_OBUF.GTS.TRI ;
  wire \CS_N_0_OBUF.GTS.TRI ;
  wire \BA_1_OBUF.GTS.TRI ;
  wire \BA_0_OBUF.GTS.TRI ;
  wire \SA_11_OBUF.GTS.TRI ;
  wire \SA_10_OBUF.GTS.TRI ;
  wire \SA_9_OBUF.GTS.TRI ;
  wire \SA_8_OBUF.GTS.TRI ;
  wire \SA_7_OBUF.GTS.TRI ;
  wire \SA_6_OBUF.GTS.TRI ;
  wire \SA_5_OBUF.GTS.TRI ;
  wire \SA_4_OBUF.GTS.TRI ;
  wire \SA_3_OBUF.GTS.TRI ;
  wire \SA_2_OBUF.GTS.TRI ;
  wire \SA_1_OBUF.GTS.TRI ;
  wire \SA_0_OBUF.GTS.TRI ;
  wire VCC;
  wire GND;
  wire \NlwInverterSignal_WE_N_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_do_refresh_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_RAS_N_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_CM_ACK_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_do_load_mode_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_OE_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_do_precharge_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_REF_ACK_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_do_reada_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_CAS_N_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_do_writea_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_do_nop_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_CKE_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_CS_N_1_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_CS_N_0_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_BA_1_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_BA_0_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_SA_11_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_SA_10_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_SA_9_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_SA_8_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_SA_7_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_SA_6_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_SA_5_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_SA_4_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_SA_3_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_SA_2_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_SA_1_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_SA_0_OBUF.GTS.TRI/CTL ;
  wire [3 : 0] rp_shift;
  wire [7 : 0] command_delay;
  wire [3 : 0] oe_shift;
  wire [1 : 0] rw_shift;
  defparam SA_9_0.INIT = 1'b0;
  X_SFF SA_9_0 (
    .I(SADDR_17_IBUF),
    .SRST(_n0116),
    .CLK(CLK_BUFGP),
    .O(SA_9),
    .CE(VCC),
    .SET(GND),
    .RST(GSR),
    .SSET(GND)
  );
  defparam _n01161.INIT = 8'h57;
  X_LUT3 _n01161 (
    .ADR0(RESET_N_IBUF),
    .ADR1(do_reada_1),
    .ADR2(do_writea_1),
    .O(_n0116)
  );
  defparam SA_10_1.INIT = 1'b0;
  X_SFF SA_10_1 (
    .I(_n0044),
    .SRST(CS_N_0_N342),
    .CLK(CLK_BUFGP),
    .O(SA_10),
    .CE(VCC),
    .SET(GND),
    .RST(GSR),
    .SSET(GND)
  );
  X_ONE XST_VCC (
    .O(N312)
  );
  defparam _n01631.INIT = 4'h5;
  X_LUT2 _n01631 (
    .ADR0(SADDR_21_IBUF),
    .O(_n0163),
    .ADR1(GND)
  );
  defparam BA_0_2.INIT = 1'b0;
  X_SFF BA_0_2 (
    .I(SADDR_19_IBUF),
    .SRST(_n0053),
    .CLK(CLK_BUFGP),
    .O(BA_0),
    .CE(VCC),
    .SET(GND),
    .RST(GSR),
    .SSET(GND)
  );
  defparam _n01461.INIT = 16'h888D;
  X_LUT4 _n01461 (
    .ADR0(do_refresh_OBUF),
    .ADR1(REF_REQ_IBUF),
    .ADR2(do_load_mode_OBUF),
    .ADR3(N3533),
    .O(_n0146)
  );
  defparam _n0033_inst_inv_01.INIT = 4'hD;
  X_LUT2 _n0033_inst_inv_01 (
    .ADR0(SC_RC_1_IBUF),
    .ADR1(SC_RC_0_IBUF),
    .O(_n0033_inst_inv_0)
  );
  defparam _n01221.INIT = 16'h0001;
  X_LUT4 _n01221 (
    .ADR0(_n0064),
    .ADR1(_n0090),
    .ADR2(_n0061),
    .ADR3(N3555),
    .O(_n0122)
  );
  defparam _n012132.INIT = 16'h0002;
  X_LUT4 _n012132 (
    .ADR0(CHOICE109),
    .ADR1(_n0090),
    .ADR2(_n0061),
    .ADR3(_n0062),
    .O(_n0121)
  );
  defparam _n01201.INIT = 16'hAAAB;
  X_LUT4 _n01201 (
    .ADR0(_n0090),
    .ADR1(_n0061),
    .ADR2(_n0065),
    .ADR3(N3480),
    .O(_n0120)
  );
  defparam _n01181.INIT = 16'h2223;
  X_LUT4 _n01181 (
    .ADR0(_n0061),
    .ADR1(_n0090),
    .ADR2(_n0065),
    .ADR3(N3484),
    .O(_n0118)
  );
  defparam SA_5_3.INIT = 1'b0;
  X_SFF SA_5_3 (
    .I(_n0047),
    .SRST(CS_N_0_N342),
    .CLK(CLK_BUFGP),
    .O(SA_5),
    .CE(VCC),
    .SET(GND),
    .RST(GSR),
    .SSET(GND)
  );
  defparam CM_ACK_ClkEn_INV1.INIT = 4'h7;
  X_LUT2 CM_ACK_ClkEn_INV1 (
    .ADR0(do_refresh_OBUF),
    .ADR1(REF_REQ_IBUF),
    .O(CM_ACK_N329)
  );
  defparam command_delay_2.INIT = 1'b0;
  X_FF command_delay_2 (
    .I(_n0016),
    .RST(\command_delay_2.GSR.OR ),
    .CLK(CLK_BUFGP),
    .O(command_delay[2]),
    .CE(VCC),
    .SET(GND)
  );
  defparam OE_N3291.INIT = 4'h5;
  X_LUT2 OE_N3291 (
    .ADR0(do_writea_1),
    .O(OE_N329),
    .ADR1(GND)
  );
  defparam rp_done_4.INIT = 1'b0;
  X_FF rp_done_4 (
    .I(_n0024),
    .RST(\rp_done.GSR.OR ),
    .CLK(CLK_BUFGP),
    .O(rp_done),
    .CE(VCC),
    .SET(GND)
  );
  defparam SA_1_5.INIT = 1'b0;
  X_SFF SA_1_5 (
    .I(_n0051),
    .SRST(CS_N_0_N342),
    .CLK(CLK_BUFGP),
    .O(SA_1),
    .CE(VCC),
    .SET(GND),
    .RST(GSR),
    .SSET(GND)
  );
  defparam RAS_N_6.INIT = 1'b1;
  X_SFF RAS_N_6 (
    .I(_n0057),
    .SSET(CS_N_0_N342),
    .CLK(CLK_BUFGP),
    .O(RAS_N_OBUF),
    .CE(VCC),
    .SET(GSR),
    .RST(GND),
    .SRST(GND)
  );
  defparam command_delay_5.INIT = 1'b0;
  X_FF command_delay_5 (
    .I(_n0013),
    .RST(\command_delay_5.GSR.OR ),
    .CLK(CLK_BUFGP),
    .O(command_delay[5]),
    .CE(VCC),
    .SET(GND)
  );
  defparam command_delay_4.INIT = 1'b0;
  X_FF command_delay_4 (
    .I(_n0014),
    .RST(\command_delay_4.GSR.OR ),
    .CLK(CLK_BUFGP),
    .O(command_delay[4]),
    .CE(VCC),
    .SET(GND)
  );
  defparam command_delay_3.INIT = 1'b0;
  X_FF command_delay_3 (
    .I(_n0015),
    .RST(\command_delay_3.GSR.OR ),
    .CLK(CLK_BUFGP),
    .O(command_delay[3]),
    .CE(VCC),
    .SET(GND)
  );
  defparam SA_11_7.INIT = 1'b0;
  X_SFF SA_11_7 (
    .I(SADDR_19_IBUF),
    .SRST(_n0116),
    .CLK(CLK_BUFGP),
    .O(SA_11),
    .CE(VCC),
    .SET(GND),
    .RST(GSR),
    .SSET(GND)
  );
  defparam rp_shift_0.INIT = 1'b0;
  X_FF rp_shift_0 (
    .I(_n0023),
    .RST(\rp_shift_0.GSR.OR ),
    .CLK(CLK_BUFGP),
    .O(rp_shift[0]),
    .CE(VCC),
    .SET(GND)
  );
  defparam rp_shift_1.INIT = 1'b0;
  X_FF rp_shift_1 (
    .I(_n0022),
    .RST(\rp_shift_1.GSR.OR ),
    .CLK(CLK_BUFGP),
    .O(rp_shift[1]),
    .CE(VCC),
    .SET(GND)
  );
  defparam SA_0_8.INIT = 1'b0;
  X_SFF SA_0_8 (
    .I(_n0052),
    .SRST(CS_N_0_N342),
    .CLK(CLK_BUFGP),
    .O(SA_0),
    .CE(VCC),
    .SET(GND),
    .RST(GSR),
    .SSET(GND)
  );
  defparam do_precharge_9.INIT = 1'b0;
  X_FF do_precharge_9 (
    .I(_n0064),
    .CE(_n0121),
    .RST(\do_precharge.GSR.OR ),
    .CLK(CLK_BUFGP),
    .O(do_precharge_OBUF),
    .SET(GND)
  );
  defparam rp_shift_2.INIT = 1'b0;
  X_FF rp_shift_2 (
    .I(_n0021),
    .RST(\rp_shift_2.GSR.OR ),
    .CLK(CLK_BUFGP),
    .O(rp_shift[2]),
    .CE(VCC),
    .SET(GND)
  );
  defparam BA_1_10.INIT = 1'b0;
  X_SFF BA_1_10 (
    .I(SADDR_20_IBUF),
    .SRST(_n0053),
    .CLK(CLK_BUFGP),
    .O(BA_1),
    .CE(VCC),
    .SET(GND),
    .RST(GSR),
    .SSET(GND)
  );
  defparam rp_shift_3.INIT = 1'b0;
  X_FF rp_shift_3 (
    .I(_n0066),
    .RST(\rp_shift_3.GSR.OR ),
    .CLK(CLK_BUFGP),
    .O(rp_shift[3]),
    .CE(VCC),
    .SET(GND)
  );
  defparam CS_N_1_11.INIT = 1'b0;
  X_SFF CS_N_1_11 (
    .I(_n0163),
    .SRST(_n0054),
    .CLK(CLK_BUFGP),
    .O(CS_N_1),
    .CE(VCC),
    .SET(GND),
    .RST(GSR),
    .SSET(GND)
  );
  defparam do_writea_12.INIT = 1'b0;
  X_FF do_writea_12 (
    .I(_n0062),
    .CE(_n0119),
    .RST(\do_writea.GSR.OR ),
    .CLK(CLK_BUFGP),
    .O(do_writea_OBUF),
    .SET(GND)
  );
  defparam do_refresh_13.INIT = 1'b0;
  X_FF do_refresh_13 (