vhdl 文本文档.txt

来自「用ＭＡＸＰＬＵＳ设计的ＣＭＩ程序」· 文本 代码 · 共 56 行

--shiyanbufen VHDLdaima--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity cmi is
   port( clk    :   in   std_logic;
         key    :   in   std_logic_vector(7 downto 0);
         cmiin  :   in   std_logic;
         cmiout :  out   std_logic;
         sout   :  out   std_logic);
end cmi;
architecture behave of cmi is
  signal sin:     std_logic;
  signal scount:  std_logic_vector(2 downto 0);
  signal cmi_temp: std_logic;
  signal cme_out : std_logic;
  signal s1,s2   :std_logic;
  begin
  process(clk)
    begin
      if(clk'event and clk='1') then
         scount<=scount+1;
         case(scount) is
           when "000"=>sin<=key(1);
                 ......
           when "111"=>sin<=key(0);
           when others=>sin<='0';
         end case;
         cmi_temp<=not cmi_temp;
       end if;
  end process;
  process(clk,scount)
    begin
      if(sin='1') then
         cmiout<=cmi_temp;
      else
         cmiout<=not clk;
      end if;
  end process;
  process(clk)
    begin
      if(clk'event and clk='1') then
         s1<=cmiin;
      end if;
      if(clk'event and clk='0') then 
         s2<=cmiin;
      end if;
  end process;
  process(clk)
    begin 
      if(clk'event and clk='0') then
         sout<=not (s1 xor s2);
      end if;
  end process;
end behave;