📄 cmi.rpt
字号:
- 7 - A 07 OR2 ! 2 2 0 1 |74151:2|f74151:sub|:73
- 8 - A 07 OR2 ! 2 2 0 1 |74151:2|f74151:sub|:74
- 6 - A 07 OR2 ! 0 3 0 1 |74151:2|f74151:sub|:78
- 3 - A 07 OR2 ! 0 4 1 1 |74151:2|f74151:sub|:81
- 7 - A 01 OR2 1 2 1 0 |74157:18|Y1 (|74157:18|:22)
- 2 - A 09 DFFE + 0 0 0 6 |74161:30|f74161:sub|QA (|74161:30|f74161:sub|:9)
- 1 - A 07 DFFE + 0 1 0 4 |74161:30|f74161:sub|QB (|74161:30|f74161:sub|:87)
- 2 - A 07 DFFE + 0 2 0 1 |74161:30|f74161:sub|QC (|74161:30|f74161:sub|:99)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\zzh-project\eda2003\vhdl\cmi\cmi.rpt
cmi
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 6/ 96( 6%) 1/ 48( 2%) 0/ 48( 0%) 4/16( 25%) 2/16( 12%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\zzh-project\eda2003\vhdl\cmi\cmi.rpt
cmi
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 clk
Device-Specific Information: d:\zzh-project\eda2003\vhdl\cmi\cmi.rpt
cmi
** EQUATIONS **
clk : INPUT;
cmi_in : INPUT;
K0 : INPUT;
K1 : INPUT;
K2 : INPUT;
K3 : INPUT;
K4 : INPUT;
K5 : INPUT;
K6 : INPUT;
K7 : INPUT;
-- Node name is 'cmi_out'
-- Equation name is 'cmi_out', type is output
cmi_out = _LC7_A1;
-- Node name is 'Dout'
-- Equation name is 'Dout', type is output
Dout = _LC6_C10;
-- Node name is 'temp'
-- Equation name is 'temp', type is output
temp = _LC3_A7;
-- Node name is '|7474:19|:9' = '|7474:19|1Q'
-- Equation name is '_LC1_A1', type is buried
_LC1_A1 = DFFE(!_LC1_A1, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is '|7474:19|:10' = '|7474:19|2Q'
-- Equation name is '_LC6_C10', type is buried
_LC6_C10 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !_LC1_C10 & _LC2_C10
# _LC1_C10 & !_LC2_C10;
-- Node name is '|7474:23|:9' = '|7474:23|1Q'
-- Equation name is '_LC2_C10', type is buried
_LC2_C10 = DFFE( cmi_in, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is '|7474:23|:10' = '|7474:23|2Q'
-- Equation name is '_LC1_C10', type is buried
_LC1_C10 = DFFE( cmi_in, GLOBAL(!clk), VCC, VCC, VCC);
-- Node name is '|74151:2|f74151:sub|:67'
-- Equation name is '_LC4_A7', type is buried
!_LC4_A7 = _LC4_A7~NOT;
_LC4_A7~NOT = LCELL( _EQ002);
_EQ002 = !K0 & !K1
# !K1 & _LC2_A9
# !K0 & !_LC2_A9;
-- Node name is '|74151:2|f74151:sub|:68'
-- Equation name is '_LC5_A7', type is buried
!_LC5_A7 = _LC5_A7~NOT;
_LC5_A7~NOT = LCELL( _EQ003);
_EQ003 = !K2 & !K3
# !K3 & _LC2_A9
# !K2 & !_LC2_A9;
-- Node name is '|74151:2|f74151:sub|:73'
-- Equation name is '_LC7_A7', type is buried
!_LC7_A7 = _LC7_A7~NOT;
_LC7_A7~NOT = LCELL( _EQ004);
_EQ004 = !K4 & !K5
# !K5 & _LC2_A9
# !K4 & !_LC2_A9
# _LC1_A7;
-- Node name is '|74151:2|f74151:sub|:74'
-- Equation name is '_LC8_A7', type is buried
!_LC8_A7 = _LC8_A7~NOT;
_LC8_A7~NOT = LCELL( _EQ005);
_EQ005 = !K6 & !K7
# !K7 & _LC2_A9
# !K6 & !_LC2_A9
# !_LC1_A7;
-- Node name is '|74151:2|f74151:sub|:78'
-- Equation name is '_LC6_A7', type is buried
!_LC6_A7 = _LC6_A7~NOT;
_LC6_A7~NOT = LCELL( _EQ006);
_EQ006 = !_LC4_A7 & !_LC5_A7
# !_LC1_A7 & !_LC4_A7
# _LC1_A7 & !_LC5_A7;
-- Node name is '|74151:2|f74151:sub|:81'
-- Equation name is '_LC3_A7', type is buried
!_LC3_A7 = _LC3_A7~NOT;
_LC3_A7~NOT = LCELL( _EQ007);
_EQ007 = !_LC6_A7 & !_LC7_A7 & !_LC8_A7
# !_LC2_A7 & !_LC6_A7
# _LC2_A7 & !_LC7_A7 & !_LC8_A7;
-- Node name is '|74157:18|:22' = '|74157:18|Y1'
-- Equation name is '_LC7_A1', type is buried
_LC7_A1 = LCELL( _EQ008);
_EQ008 = clk & !_LC3_A7
# _LC1_A1 & _LC3_A7;
-- Node name is '|74161:30|f74161:sub|:9' = '|74161:30|f74161:sub|QA'
-- Equation name is '_LC2_A9', type is buried
_LC2_A9 = DFFE(!_LC2_A9, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is '|74161:30|f74161:sub|:87' = '|74161:30|f74161:sub|QB'
-- Equation name is '_LC1_A7', type is buried
_LC1_A7 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = _LC1_A7 & !_LC2_A9
# !_LC1_A7 & _LC2_A9;
-- Node name is '|74161:30|f74161:sub|:99' = '|74161:30|f74161:sub|QC'
-- Equation name is '_LC2_A7', type is buried
_LC2_A7 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = !_LC1_A7 & _LC2_A7
# _LC2_A7 & !_LC2_A9
# _LC1_A7 & !_LC2_A7 & _LC2_A9;
Project Information d:\zzh-project\eda2003\vhdl\cmi\cmi.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 52,034K
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