hardware.h

MICREL 网卡驱动 FOR CE 5.0

/* P3CR2                   0x0542 */
/* P3VIDCR                 0x0544 */
/* P3CR3                   0x0546 */
/* P3IRCR                  0x0548 */
/* P3ERCR                  0x054A */
/* P3SR                    0x0554 */

/* -------------------------------------------------------------------------- */

#ifdef KS_ISA_BUS
#ifdef INLINE
#ifdef SH_16BIT_WRITE
#define HardwareSelectBank( pHardware, bBank )                              \
{                                                                           \
    HW_WRITE_WORD( pHardware, REG_BANK_SEL_OFFSET, bBank );                 \
    ( pHardware )->m_bBank = bBank;                                         \
}

#else
#define HardwareSelectBank( pHardware, bBank )                              \
{                                                                           \
    HW_WRITE_BYTE( pHardware, REG_BANK_SEL_OFFSET, bBank );                 \
    ( pHardware )->m_bBank = bBank;                                         \
}
#endif

#define HardwareReadRegByte( pHardware, bBank, bOffset, pbData )            \
{                                                                           \
    if ( ( bBank ) != ( pHardware )->m_bBank )                              \
        HardwareSelectBank( pHardware, bBank );                             \
    HW_READ_BYTE( pHardware, bOffset, pbData );                             \
}

#define HardwareWriteRegByte( pHardware, bBank, bOffset, bValue )           \
{                                                                           \
    if ( ( bBank ) != ( pHardware )->m_bBank )                              \
        HardwareSelectBank( pHardware, bBank );                             \
    HW_WRITE_BYTE( pHardware, bOffset, bValue );                            \
}

#define HardwareReadRegWord( pHardware, bBank, bOffset, pwData )            \
{                                                                           \
    if ( ( bBank ) != ( pHardware )->m_bBank )                              \
        HardwareSelectBank( pHardware, bBank );                             \
    HW_READ_WORD( pHardware, bOffset, pwData );                             \
}

#define HardwareWriteRegWord( pHardware, bBank, bOffset, wValue )           \
{                                                                           \
    if ( ( bBank ) != ( pHardware )->m_bBank )                              \
        HardwareSelectBank( pHardware, bBank );                             \
    HW_WRITE_WORD( pHardware, bOffset, wValue );                            \
}

#define HardwareReadRegDWord( pHardware, bBank, bOffset, pwData )           \
{                                                                           \
    if ( ( bBank ) != ( pHardware )->m_bBank )                              \
        HardwareSelectBank( pHardware, bBank );                             \
    HW_READ_DWORD( pHardware, bOffset, pwData );                            \
}

#define HardwareWriteRegDWord( pHardware, bBank, bOffset, wValue )          \
{                                                                           \
    if ( ( bBank ) != ( pHardware )->m_bBank )                              \
        HardwareSelectBank( pHardware, bBank );                             \
    HW_WRITE_DWORD( pHardware, bOffset, wValue );                           \
}

#ifdef SH_32BIT_ACCESS_ONLY
#define HardwareWriteIntMask( pHardware, ulValue )                          \
{                                                                           \
    if ( REG_INT_MASK_BANK != ( pHardware )->m_bBank )                      \
        HardwareSelectBank( pHardware, REG_INT_MASK_BANK );                 \
    HW_WRITE_DWORD( pHardware, REG_INT_MASK_OFFSET, ulValue );              \
}

#define HardwareWriteIntStat( pHardware, ulValue )                          \
{                                                                           \
    ULONG ulIntEnable;                                                      \
    if ( REG_INT_STATUS_BANK != ( pHardware )->m_bBank )                    \
        HardwareSelectBank( pHardware, REG_INT_STATUS_BANK );               \
    HW_READ_DWORD( pHardware, REG_INT_MASK_OFFSET, &ulIntEnable );          \
    ulIntEnable &= 0x0000FFFF;                                              \
    ulIntEnable |= ulValue;                                                 \
    HW_WRITE_DWORD( pHardware, REG_INT_MASK_OFFSET, ulIntEnable );          \
}
#endif

#else
void HardwareSelectBank (
    PHARDWARE pHardware,
    UCHAR     bBank );

void HardwareReadRegByte (
    PHARDWARE pHardware,
    UCHAR     bBank,
    UCHAR     bOffset,
    PUCHAR    pbData );

void HardwareReadRegWord (
    PHARDWARE pHardware,
    UCHAR     bBank,
    UCHAR     bOffset,
    PUSHORT   pwData );

void HardwareReadRegDWord (
    PHARDWARE pHardware,
    UCHAR     bBank,
    UCHAR     bOffset,
    PULONG    pwData );

void HardwareWriteRegByte (
    PHARDWARE pHardware,
    UCHAR     bBank,
    UCHAR     bOffset,
    UCHAR     bData );

void HardwareWriteRegWord (
    PHARDWARE pHardware,
    UCHAR     bBank,
    UCHAR     bOffset,
    USHORT    wData );

void HardwareWriteRegDWord (
    PHARDWARE pHardware,
    UCHAR     bBank,
    UCHAR     bOffset,
    ULONG     wData );

#ifdef SH_32BIT_ACCESS_ONLY
void HardwareWriteIntMask (
    PHARDWARE pHardware,
    ULONG     ulValue );

void HardwareWriteIntStat (
    PHARDWARE pHardware,
    ULONG     ulValue );
#endif

#endif

void hw_read_dword
(
    PHARDWARE phwi,
    UCHAR     addr,
    ULONG    *data
);
void hw_write_dword
(
    PHARDWARE phwi,
    UCHAR     addr,
    ULONG     data
);

void HardwareReadBuffer (
    PHARDWARE pHardware,
    UCHAR     bOffset,
    PULONG    pdwData,
    int       length );

void HardwareWriteBuffer (
    PHARDWARE pHardware,
    UCHAR     bOffset,
    PULONG    pdwData,
    int       length );


#endif

/* -------------------------------------------------------------------------- */

/*
    Initial setup routines
*/

#ifdef KS_ISA_BUS
BOOLEAN HardwareInitialize_ISA (
    PHARDWARE pHardware );

BOOLEAN HardwareReset_ISA (
    PHARDWARE pHardware );

void HardwareSetup_ISA (
    PHARDWARE pHardware );

void HardwareSetupFunc_ISA (
    struct hw_fn* ks8842_fn );

void HardwareSetupInterrupt_ISA (
    PHARDWARE pHardware );

BOOLEAN HardwareSetBurst (
    PHARDWARE pHardware,
    UCHAR     bBurstLength );

#endif

#ifdef KS_PCI
#ifdef DBG
void CheckDescriptors (
    PTDescInfo pInfo );
#endif

void CheckDescriptorNum (
    PTDescInfo pInfo );

BOOLEAN HardwareInitialize_PCI (
    PHARDWARE pHardware );

BOOLEAN HardwareReset_PCI (
    PHARDWARE pHardware );

void HardwareSetup_PCI (
    PHARDWARE pHardware );

void HardwareSetupFunc_PCI (
    struct hw_fn* ks8842_fn );

void HardwareSetupInterrupt_PCI (
    PHARDWARE pHardware );
#endif

void HardwareSwitchSetup
(
    PHARDWARE pHardware );


void HardwareReadChipID
(
    PHARDWARE pHardware,
    PUSHORT   pChipID,
    PUCHAR    pDevRevisionID
);

#ifdef KS_PCI_BUS
#define HardwareInitialize      HardwareInitialize_PCI
#define HardwareReset           HardwareReset_PCI
#define HardwareSetup           HardwareSetup_PCI
#define HardwareSetupFunc       HardwareSetupFunc_PCI
#define HardwareSetupInterrupt  HardwareSetupInterrupt_PCI

#else
#define HardwareInitialize      HardwareInitialize_ISA
#define HardwareReset           HardwareReset_ISA
#define HardwareSetup           HardwareSetup_ISA
#define HardwareSetupFunc       HardwareSetupFunc_ISA
#define HardwareSetupInterrupt  HardwareSetupInterrupt_ISA
#endif

/* -------------------------------------------------------------------------- */

/*
    Link processing primary routines
*/

#ifdef KS_ISA_BUS
#ifdef INLINE
#ifdef SH_32BIT_ACCESS_ONLY
#define HardwareAcknowledgeLink_ISA( pHardware )                            \
{                                                                           \
    HardwareWriteIntStat( pHardware, INT_STATUS( INT_PHY ));                \
}
#else
#define HardwareAcknowledgeLink_ISA( pHardware )                            \
{                                                                           \
    HardwareWriteRegWord( pHardware, REG_INT_STATUS_BANK,                   \
        REG_INT_STATUS_OFFSET, INT_PHY );                                   \
}
#endif

#else
void HardwareAcknowledgeLink_ISA (
    PHARDWARE pHardware );
#endif

void HardwareCheckLink_ISA (
    PHARDWARE pHardware );
#endif

#ifdef KS_PCI_BUS
#ifdef INLINE
#define HardwareAcknowledgeLink_PCI( pHardware )                            \
{                                                                           \
    HW_WRITE_DWORD( pHardware, REG_INTERRUPTS_STATUS, INT_PHY );            \
}

#else
void HardwareAcknowledgeLink_PCI (
    PHARDWARE pHardware );
#endif

void HardwareCheckLink_PCI (
    PHARDWARE pHardware );
#endif

#ifdef KS_PCI_BUS
#define HardwareAcknowledgeLink  HardwareAcknowledgeLink_PCI
#define HardwareCheckLink        HardwareCheckLink_PCI

#else
#define HardwareAcknowledgeLink  HardwareAcknowledgeLink_ISA
#define HardwareCheckLink        HardwareCheckLink_ISA
#endif

/* -------------------------------------------------------------------------- */

/*
    Receive processing primary routines
*/

#ifdef KS_ISA_BUS
#ifdef INLINE
#define HardwareReleaseReceive_ISA( pHardware )                             \
{                                                                           \
    HardwareWriteRegByte( pHardware, REG_RXQ_CMD_BANK, REG_RXQ_CMD_OFFSET,  \
                          RXQ_CMD_FREE_PACKET );                            \
}

#ifdef SH_32BIT_ACCESS_ONLY
#define HardwareAcknowledgeReceive_ISA( pHardware )                         \
{                                                                           \
    HardwareWriteIntStat( pHardware, INT_STATUS( INT_RX ));                 \
}
#else
#define HardwareAcknowledgeReceive_ISA( pHardware )                         \
{                                                                           \
    HardwareWriteRegWord( pHardware, REG_INT_STATUS_BANK, REG_INT_STATUS_OFFSET,  \
                          INT_RX );                                         \
}
#endif

#else

void HardwareReleaseReceive_ISA (
    PHARDWARE pHardware );

void HardwareAcknowledgeReceive_ISA (
    PHARDWARE pHardware );
#endif

void HardwareStartReceive_ISA (
    PHARDWARE pHardware );

void HardwareStopReceive_ISA (
    PHARDWARE pHardware );

#endif /* #ifdef INLINE */

#ifdef KS_PCI_BUS
#ifdef INLINE
#define HardwareAcknowledgeReceive_PCI( pHardware )                         \
{                                                                           \
    HW_WRITE_DWORD( pHardware, REG_INTERRUPTS_STATUS, INT_RX );             \
}

#else
void HardwareReleaseReceive_PCI (
    PHARDWARE pHardware );

void HardwareAcknowledgeReceive_PCI (
    PHARDWARE pHardware );
#endif

#define HardwareResumeReceive( pHardware )                                  \
{                                                                           \
    HW_WRITE_DWORD( pHardware, REG_DMA_RX_START, DMA_START );               \
}

void HardwareStartReceive_PCI (
    PHARDWARE pHardware );

void HardwareStopReceive_PCI (
    PHARDWARE pHardware );
#endif

#ifdef KS_PCI_BUS
#define HardwareReleaseReceive      HardwareReleaseReceive_PCI
#define HardwareAcknowledgeReceive  HardwareAcknowledgeReceive_PCI
#define HardwareStartReceive        HardwareStartReceive_PCI
#define HardwareStopReceive         HardwareStopReceive_PCI

#else
#define HardwareReleaseReceive      HardwareReleaseReceive_ISA
#define HardwareAcknowledgeReceive  HardwareAcknowledgeReceive_ISA
#define HardwareStartReceive        HardwareStartReceive_ISA
#define HardwareStopReceive         HardwareStopReceive_IS