hardware.h

MICREL 网卡驱动 FOR CE 5.0

#define INT_WAN_TX_BUF_UNAVAIL      0x10000000
#define INT_WAN_RX                  0x20000000
#define INT_WAN_TX                  0x40000000
#define INT_WAN_PHY                 0x80000000

#define INT_RX_STOPPED              INT_WAN_RX_STOPPED
#define INT_TX_STOPPED              INT_WAN_TX_STOPPED
#define INT_RX_OVERRUN              INT_WAN_RX_BUF_UNAVAIL
#define INT_TX_UNDERRUN             INT_WAN_TX_BUF_UNAVAIL
#define INT_TX_EMPTY                INT_WAN_TX_BUF_UNAVAIL
#define INT_RX                      INT_WAN_RX
#define INT_TX                      INT_WAN_TX
#define INT_PHY                     INT_WAN_PHY
#define INT_MASK                    ( INT_RX | INT_TX | INT_TX_EMPTY | INT_RX_STOPPED | INT_TX_STOPPED )


/* MAC Addition Station Address */

/* MAAL0 */
#define REG_ADD_ADDR_0_LO           0x0080
/* MAAH0 */
#define REG_ADD_ADDR_0_HI           0x0084
/* MAAL1 */
#define REG_ADD_ADDR_1_LO           0x0088
/* MAAH1 */
#define REG_ADD_ADDR_1_HI           0x008C
/* MAAL2 */
#define REG_ADD_ADDR_2_LO           0x0090
/* MAAH2 */
#define REG_ADD_ADDR_2_HI           0x0094
/* MAAL3 */
#define REG_ADD_ADDR_3_LO           0x0098
/* MAAH3 */
#define REG_ADD_ADDR_3_HI           0x009C
/* MAAL4 */
#define REG_ADD_ADDR_4_LO           0x00A0
/* MAAH4 */
#define REG_ADD_ADDR_4_HI           0x00A4
/* MAAL5 */
#define REG_ADD_ADDR_5_LO           0x00A8
/* MAAH5 */
#define REG_ADD_ADDR_5_HI           0x00AC
/* MAAL6 */
#define REG_ADD_ADDR_6_LO           0x00B0
/* MAAH6 */
#define REG_ADD_ADDR_6_HI           0x00B4
/* MAAL7 */
#define REG_ADD_ADDR_7_LO           0x00B8
/* MAAH7 */
#define REG_ADD_ADDR_7_HI           0x00BC
/* MAAL8 */
#define REG_ADD_ADDR_8_LO           0x00C0
/* MAAH8 */
#define REG_ADD_ADDR_8_HI           0x00C4
/* MAAL9 */
#define REG_ADD_ADDR_9_LO           0x00C8
/* MAAH9 */
#define REG_ADD_ADDR_9_HI           0x00CC
/* MAAL10 */
#define REG_ADD_ADDR_A_LO           0x00D0
/* MAAH10 */
#define REG_ADD_ADDR_A_HI           0x00D4
/* MAAL11 */
#define REG_ADD_ADDR_B_LO           0x00D8
/* MAAH11 */
#define REG_ADD_ADDR_B_HI           0x00DC
/* MAAL12 */
#define REG_ADD_ADDR_C_LO           0x00E0
/* MAAH12 */
#define REG_ADD_ADDR_C_HI           0x00E4
/* MAAL13 */
#define REG_ADD_ADDR_D_LO           0x00E8
/* MAAH13 */
#define REG_ADD_ADDR_D_HI           0x00EC
/* MAAL14 */
#define REG_ADD_ADDR_E_LO           0x00F0
/* MAAH14 */
#define REG_ADD_ADDR_E_HI           0x00F4
/* MAAL15 */
#define REG_ADD_ADDR_F_LO           0x00F8
/* MAAH15 */
#define REG_ADD_ADDR_F_HI           0x00FC

#define ADD_ADDR_HI_MASK            0x00FF
#define ADD_ADDR_ENABLE             0x8000

/* Miscellaneour Registers */

/* MARL */
#define REG_ADDR_0_OFFSET           0x0200
#define REG_ADDR_1_OFFSET           0x0201
/* MARM */
#define REG_ADDR_2_OFFSET           0x0202
#define REG_ADDR_3_OFFSET           0x0203
/* MARH */
#define REG_ADDR_4_OFFSET           0x0204
#define REG_ADDR_5_OFFSET           0x0205

/* OBCR */
#define REG_BUS_CTRL_OFFSET         0x0210

/* EEPCR */
#define REG_EEPROM_CTRL_OFFSET      0x0212

/* MBIR */
#define REG_MEM_INFO_OFFSET         0x0214

/* GCR */
#define REG_GLOBAL_CTRL_OFFSET      0x0216


/* WFCR */
#define REG_WOL_CTRL_OFFSET         0x021A

/* WF0 */

#define WOL_FRAME_CRC_OFFSET        0x0220
#define WOL_FRAME_BYTE0_OFFSET      0x0224
#define WOL_FRAME_BYTE2_OFFSET      0x0228


#endif /* #ifdef KS_PCI_BUS */

/*
 * ks884x Registers Bit definitions
 *
 *  Note: these bit definitions can be used by both ISA_BUS or PCI_BUS interface.
 */

/* Receive Descriptor */
#define DESC_OWN_BIT            0x80000000      /* Descriptor own bit, 1: own by ks884x, 0: own by host */

#define RFC_FS                  0x40000000      /* First Descriptor of the received frame */
#define RFC_LS                  0x20000000      /* Last Descriptor of the received frame */
#define RFC_IPE                 0x10000000      /* IP checksum generation */
#define RFC_TCPE                0x08000000      /* TCP checksum generation */
#define RFC_UDPE                0x04000000      /* UDP checksum generation */
#define RFC_ES                  0x02000000      /* Error Summary */
#define RFC_MF                  0x01000000      /* Multicast Frame */
#define RFC_RE                  0x00080000      /* Report on MII/GMII error */
#define RFC_TL                  0x00040000      /* Frame Too Long */
#define RFC_RF                  0x00020000      /* Runt Frame */
#define RFC_CRC                 0x00010000      /* CRC error */
#define RFC_FT                  0x00008000      /* Frame Type */
#define RFC_FL_MASK             0x000007ff      /* Frame Length bit mask, 0:10 */

#ifdef RCV_HUGE_FRAME
#define RFC_ERROR_MASK          (RFC_IPE | RFC_TCPE | RFC_UDPE | RFC_RE | RFC_CRC | RFC_RF )
#else
#define RFC_ERROR_MASK          (RFC_IPE | RFC_TCPE | RFC_UDPE | RFC_RE | RFC_CRC | RFC_RF | RFC_TL  )
#endif

/* Transmit Descriptor */
#define TFC_IC                  0x80000000      /* Interrupt on completion */
#define TFC_FS                  0x40000000      /* first segment */
#define TFC_LS                  0x20000000      /* last segment */
#define TFC_IPCKG               0x10000000      /* IP checksum generation */
#define TFC_TCPCKG              0x08000000      /* TCP checksum generation */
#define TFC_UDPCKG              0x04000000      /* UDP checksum generation */
#define TFC_TER                 0x02000000      /* Transmit End of Ring */
#define TFC_TBS_MASK            0x000007ff      /* Transmit Buffer Size Mask (0:10) */


/* DMA Registers */

/* MDTXC                  0x0000 */
/* MDRXC                  0x0004 */
#define DMA_PBLTMASK            0x3f000000      /* DMA Burst Size bit mask */
#define DMA_UDPCHECKSUM         0x00040000      /* MAC UDP checksum enable */
#define DMA_TCPCHECKSUM         0x00020000      /* MAC TCP checksum enable */
#define DMA_IPCHECKSUM          0x00010000      /* MAC IP checksum enable  */
#define DMA_FLOWCTRL            0x00000200      /* MAC flow control enable */
#define DMA_ERRORFRAME          0x00000008      /* MAC will Rx error frame */
#define DMA_PADDING             0x00000004      /* MAC Tx enable padding   */
#define DMA_CRC                 0x00000002      /* MAC Tx add CRC          */

#define DMA_BROADCAST           0x00000040      /* MAC Rx all broadcast frame */
#define DMA_MULTICAST           0x00000020      /* MAC Rx all multicast frame */
#define DMA_UNICAST             0x00000010      /* MAC Rx only unicast frame  */
#define DMA_PROMISCUOUS         0x00000004      /* MAC Rx all all frame       */

/* MDTSC                  0x0008 */
/* MDRSC                  0x000C */
#define DMA_START               0x00000001      /* DMA start command */

/* TDLB                   0x0010 */
/* RDLB                   0x0014 */

/* MTR0                   0x0020 */
/* MTR1                   0x0024 */



/* Interrupt Registers */

/* INTEV                   0x0028 */
/* INTST                   0x002C */
#define INT_TX_DONE             0x40000000      /* Enable Tx completed bit */
#define INT_RX_FRAME            0x20000000      /* Enable Rx at lease a frame bit */
#define INT_TX_STOP             0x04000000      /* Enable Tx stop bit */
#define INT_RX_STOP             0x02000000      /* Enable Tx stop bit */

/* MAC Addition Station Address */

/* MAAL0                   0x0080 */
/* MAAH0                   0x0084 */
#define MAC_ADDR_ENABLE         0x80000000      /* This MAC table entry is Enabled */

/* Miscellaneour Registers */

/* MARL                    0x0200 */
/* MARM                    0x0202 */
/* MARH                    0x0204 */
/* OBCR                    0x0210 */
/* EEPCR                   0x0212 */
/* MBIR                    0x0214 */

/* GCR                     0x0216 */
#define GLOBAL_SOFTWARE_RESET   0x0001      /* pass all frames */

/* Switch Registers */

/* SIDER                   0x0400 */
#define SW_ENABLE               0x0001      /* enable switch */

/* SGCR1                   0x0402 */
#define SW_PASS_ALL_FRAMES      0x8000      /* pass all frames */
#define SW_IEEE_TX_FLOWCNTL     0x2000      /* IEEE 802.3x Tx flow control enable */
#define SW_IEEE_RX_FLOWCNTL     0x1000      /* IEEE 802.3x Rx flow control enable */
#define SW_FRAME_LEN_CHECK      0x0800      /* frame length field check */
#define SW_AGING_ENABLE         0x0400      /* Aging enable */
#define SW_FAST_AGING           0x0200      /* Fast Age enable */
#define SW_BACKOFF_EN           0x0100      /* aggressive back off enable */
#define SW_UNH_BACKOFF_EN       0x0080      /* new backoff enable for UNH */
#define SW_PASS_FLOWCNTL_FRAMES 0x0008      /* NOT filter 802.1x flow control packets */
#define SW_BUFFER_SHARE         0x0004      /* buffer share mode */
#define SW_AUTO_FAST_AGING      0x0001      /* automic fast aging when link changed detected */

/* SGCR2                   0x0404 */
#define SW_8021Q_VLAN_EN        0x8000      /* Enable IEEE 802.1Q VLAN enable */
#define SW_IGMP_SNOOP_EN        0x4000      /* Enable IGMP Snoop on switch MII interface */
#define SW_SNIFF_TX_AND_RX      0x0100      /* Sniff monitor Tx and Rx. */
#define SW_VLAN_MISMATCH_DISCARD 0x0080     /* unicast port-VLAN mismatch discard */
#define SW_NO_MCAST_STORM_INC   0x0040      /* broadcast storm protection not include multicast pkts */
#define SW_PREAMBLE_MODE        0x0020      /* carrier sense based backpressure mode */
#define SW_FLOWCTRL_FAIR        0x0010      /* flow control fair mode */
#define SW_NO_COLLISION_DROP    0x0008      /* no excessive collision drop */
#define SW_HUGE_FRAME_SIZE      0x0004      /* support huge packet size upto 1916-byte */
#define SW_NO_MAX_FRAME_SIZE    0x0002      /* NOT accept packet size upto 1536-byte */
#define SW_PRIORITY_BUF_RESERVE 0x0001      /* pre-allocated 48 buffers per port reserved for high priority pkts */

/* SGCR3                   0x0406 */
#define SW_REPEATER_MODE_EN     0x0080      /* Enable repeater mode */
#define SW_MII_HALF_DUPLEX      0x0040      /* Enable switch MII half duplex mode */
#define SW_MII_FLOW_CNTL        0x0020      /* Enable switch MII flow control */
#define SW_MII_10BT             0x0010      /* The switch MII interface is in 10Mbps mode */
#define SW_NULL_VID             0x0008      /* null VID replacement */

/* SGCR4                   0x0408 */
/* SGCR5                   0x040A */
#define SW_POWER_SAVE           0x0400      /* Enable power save mode */
#define SW_CRC_DROP             0x0200      /* drop MC loop back packets if CRCs are detected */
#define SW_TPID_MODE            0x0100      /* Special TPID mode */

/* SGCR6                   0x0410 */
/* PHAR                    0x0420 */
/* LBS21R                  0x0426 */
/* LBRCTCER                0x0428 */
/* LBRCGR                  0x042A */
/* CSCR                    0x0430 */
/* PSWIR                   0x0432 */
/* RC21R                   0x0434 */
/* RC3R                    0x0436 */
/* VMCRTCR                 0x0438 */
/* S58R                    0x0440 */
/* MVI21R                  0x0444 */
/* MM1V3IR                 0x0446 */
/* MMI32R                  0x0448 */
/* LPVI21R                 0x0450 */
/* LPM1V3IR                0x0452 */
/* LPMI32R                 0x0454 */
/* CSSR                    0x0460 */
/* ASCTR                   0x0464 */
/* MS21R                   0x0468 */
/* LPS21R                  0x046A */

/* MACAR1                  0x0470 */
/* MACAR2                  0x0472 */
/* MACAR3                  0x0474 */

/* TOSR1                   0x0480 */
/* TOSR2                   0x0482 */
/* TOSR3                   0x0484 */
/* TOSR4                   0x0486 */
/* TOSR5                   0x0488 */
/* TOSR6                   0x048A */
/* TOSR7                   0x0490 */
/* TOSR8                   0x0492 */

/* IACR                    0x04A0 */
/* IADR1                   0x04A2 */
/* IADR2                   0x04A4 */
/* IADR3                   0x04A6 */
/* IADR4                   0x04A8 */
/* IADR5                   0x04AA */

/* UDR21                   0x04B0 */
/* UDR3                    0x04B2 */

/* DTSR                    0x04C0 */
/* ATSR                    0x04C2 */
/* DTCR                    0x04C4 */
/* ATCR0                   0x04C6 */
/* ATCR1                   0x04C8 */
/* ATCR2                   0x04CA */

/* P1MBCR                  0x04D0 */
#define PHY_POWER_POWERDOWN     0x0800      /* port power down */
#define PHY_AUTO_NEGOTIATION    0x0200      /* auto-negotiation enable */

/* P1MBSR                  0x04D2 */
#define PHY_AUTONEGO_COMPLETE   0x0020      /* auto nego completed on this port */
#define PHY_LINKUP              0x0004      /* Link is up on this port */

/* PHY1ILR                 0x04D4 */
/* PHY1IHR                 0x04D6 */
/* P1ANAR                  0x04D8 */
/* P1ANLPR                 0x04DA */
#define PARTNER_100FD           0x0100      /* auto nego parterner 100 FD */
#define PARTNER_100HD           0x0080      /* auto nego parterner 100 HD */
#define PARTNER_10FD            0x0040      /* auto nego parterner 10 FD */
#define PARTNER_10HD            0x0020      /* auto nego parterner 10 HD */

/* P2MBCR                  0x04E0 */
/* P2MBSR                  0x04E2 */
/* PHY2ILR                 0x04E4 */
/* PHY2IHR                 0x04E6 */
/* P2ANAR                  0x04E8 */
/* P2ANLPR                 0x04EA */
/* P1VCT                   0x04F0 */
/* P1PHYCTRL               0x04F2 */
/* P2VCT                   0x04F4 */
/* P2PHYCTRL               0x04F6 */

/* P1CR1                   0x0500 */
#define PORT_STORM_PROCTION     0x0080      /* enable broadcast storm protection (ingress) */
#define PORT_QOS_DIFFSERV       0x0040      /* enable QoS - diffServ priority classfication */
#define PORT_QOS_8021P          0x0020      /* enable QoS - 802.1P priority classfication */
#define PORT_TAG_INSERT         0x0004      /* enable VLAN tag insert to the packet (egress) */
#define PORT_TAG_REMOVE         0x0002      /* enable VLAN tag remove from the packet (egress) */
#define PORT_MULTIPLE_Q         0x0001      /* output queue is split into four queues (egress) */

/* P1CR2                   0x0502 */

/* P1VIDCR                 0x0504 */
/* P1CR3                   0x0506 */
/* P1IRCR                  0x0508 */
/* P1ERCR                  0x050A */
/* P1SCSLMD                0x0510 */
/* P1CR4                   0x0512 */
#define PORT_AUTONEGO_RESTART   0x2000      /* auto nego restart */
#define PORT_AUTONEGO_ENABLE    0x0080      /* auto nego enable */
#define PORT_AUTONEGO_ADV_PUASE 0x0010      /* auto nego advertise PAUSE */
#define PORT_AUTONEGO_ADV_100FD 0x0008      /* auto nego advertise 100 FD */
#define PORT_AUTONEGO_ADV_100HD 0x0004      /* auto nego advertise 100 HD */
#define PORT_AUTONEGO_ADV_10FD  0x0002      /* auto nego advertise 10 FD */
#define PORT_AUTONEGO_ADV_10HD  0x0001      /* auto nego advertise 10 HD */
#define PORT_AUTONEGO_ADV_MASK  0x209F

#define PORT_DISABLE_AUTONEG    0x0000      /* port disable auto nego */
#define PORT_100BASE            0x0040      /* force 100 when auto nego disabled */
#define PORT_FULLDUPLEX         0x0020      /* force full duplex when auto nego disabled */
#define PORT_MEDIA_MASK         0x0060

/* P1SR                    0x0514 */
#define PORT_DUPLEX_FULL        0x0400      /* auto nego duplex status (solved) */
#define PORT_SPEED_100BT        0x0200      /* auto nego speed status (solved) */

/* P2CR1                   0x0520 */
/* P2CR2                   0x0522 */
/* P2VIDCR                 0x0524 */
/* P2CR3                   0x0526 */
/* P2IRCR                  0x0528 */
/* P2ERCR                  0x052A */
/* P2SCSLMD                0x0530 */
/* P2CR4                   0x0532 */
/* P2SR                    0x0534 */

/* P3CR1                   0x0540 */