hardware.h

MICREL 网卡驱动 FOR CE 5.0

#define WOL_FRAME0_ENABLE       0x0001


/*
 * KS8841/KS8842 interface to Host by ISA bus.
 */

#ifdef KS_ISA_BUS

/* Bank 0 */

/* BAR */
#define REG_BASE_ADDR_BANK      0
#define REG_BASE_ADDR_OFFSET    0x00

/* BDAR */
#define REG_RX_WATERMARK_BANK   0
#define REG_RX_WATERMARK_OFFSET 0x04

#define RX_HIGH_WATERMARK_2KB   0x1000

/* BESR */
#define REG_BUS_ERROR_BANK      0
#define REG_BUS_ERROR_OFFSET    0x06

/* BBLR */
#define REG_BUS_BURST_BANK      0
#define REG_BUS_BURST_OFFSET    0x08

#define BURST_LENGTH_0          0x0000
#define BURST_LENGTH_4          0x3000
#define BURST_LENGTH_8          0x5000
#define BURST_LENGTH_16         0x7000

/* Bank 2 */

#define REG_ADDR_0_BANK         2
/* MARL */
#define REG_ADDR_0_OFFSET       0x00
#define REG_ADDR_1_OFFSET       0x01
/* MARM */
#define REG_ADDR_2_OFFSET       0x02
#define REG_ADDR_3_OFFSET       0x03
/* MARH */
#define REG_ADDR_4_OFFSET       0x04
#define REG_ADDR_5_OFFSET       0x05


/* Bank 3 */

/* OBCR */
#define REG_BUS_CTRL_BANK       3
#define REG_BUS_CTRL_OFFSET     0x00

/* EEPCR */
#define REG_EEPROM_CTRL_BANK    3
#define REG_EEPROM_CTRL_OFFSET  0x02

/* MBIR */
#define REG_MEM_INFO_BANK       3
#define REG_MEM_INFO_OFFSET     0x04

/* GCR */
#define REG_GLOBAL_CTRL_BANK    3
#define REG_GLOBAL_CTRL_OFFSET  0x06

/* WFCR */
#define REG_WOL_CTRL_BANK       3
#define REG_WOL_CTRL_OFFSET     0x0A

/* WF0 */
#define REG_WOL_FRAME_0_BANK    4
#define WOL_FRAME_CRC_OFFSET    0x00
#define WOL_FRAME_BYTE0_OFFSET  0x04
#define WOL_FRAME_BYTE2_OFFSET  0x08

/* WF1 */
#define REG_WOL_FRAME_1_BANK    5

/* WF2 */
#define REG_WOL_FRAME_2_BANK    6

/* WF3 */
#define REG_WOL_FRAME_3_BANK    7


/* Bank 16 */

/* TXCR */
#define REG_TX_CTRL_BANK        16
#define REG_TX_CTRL_OFFSET      0x00

#define TX_CTRL_ENABLE          0x0001
#define TX_CTRL_CRC_ENABLE      0x0002
#define TX_CTRL_PAD_ENABLE      0x0004
#define TX_CTRL_FLOW_ENABLE     0x0008
#define TX_CTRL_MAC_LOOPBACK    0x2000

/* TXSR */
#define REG_TX_STATUS_BANK      16
#define REG_TX_STATUS_OFFSET    0x02

#define TX_FRAME_ID_MASK        0x003F
#define TX_STAT_MAX_COL         0x1000
#define TX_STAT_LATE_COL        0x2000
#define TX_STAT_UNDERRUN        0x4000
#define TX_STAT_COMPLETE        0x8000

#ifdef EARLY_TRANSMIT
#define TX_STAT_ERRORS          ( TX_STAT_MAX_COL | TX_STAT_LATE_COL | TX_STAT_UNDERRUN )
#else
#define TX_STAT_ERRORS          ( TX_STAT_MAX_COL | TX_STAT_LATE_COL )
#endif

#define TX_CTRL_DEST_PORTS      0x0F00
#define TX_CTRL_INTERRUPT_ON    0x8000

#define TX_DEST_PORTS_SHIFT     8

#define TX_FRAME_ID_MAX         (( (TX_FRAME_ID_MASK + 1) / 2 ) - 1 )
#define TX_FRAME_ID_PORT_SHIFT  5

/* RXCR */
#define REG_RX_CTRL_BANK        16
#define REG_RX_CTRL_OFFSET      0x04

#define RX_CTRL_ENABLE          0x0001
#define RX_CTRL_MULTICAST       0x0004
#define RX_CTRL_STRIP_CRC       0x0008
#define RX_CTRL_PROMISCUOUS     0x0010
#define RX_CTRL_UNICAST         0x0020
#define RX_CTRL_ALL_MULTICAST   0x0040
#define RX_CTRL_BROADCAST       0x0080
#define RX_CTRL_BAD_PACKET      0x0200
#define RX_CTRL_FLOW_ENABLE     0x0400

/* TXMIR */
#define REG_TX_MEM_INFO_BANK    16
#define REG_TX_MEM_INFO_OFFSET  0x08

/* RXMIR */
#define REG_RX_MEM_INFO_BANK    16
#define REG_RX_MEM_INFO_OFFSET  0x0A

#define MEM_AVAILABLE_MASK      0x1FFF


/* Bank 17 */

/* TXQCR */
#define REG_TXQ_CMD_BANK        17
#define REG_TXQ_CMD_OFFSET      0x00

#define TXQ_CMD_ENQUEUE_PACKET  0x0001

/* RXQCR */
#define REG_RXQ_CMD_BANK        17
#define REG_RXQ_CMD_OFFSET      0x02

#define RXQ_CMD_FREE_PACKET     0x0001

/* TXFDPR */
#define REG_TX_ADDR_PTR_BANK    17
#define REG_TX_ADDR_PTR_OFFSET  0x04

/* RXFDPR */
#define REG_RX_ADDR_PTR_BANK    17
#define REG_RX_ADDR_PTR_OFFSET  0x06

#define ADDR_PTR_MASK           0x03FF
#define ADDR_PTR_AUTO_INC       0x4000

#define REG_DATA_BANK           17
/* QDRL */
#define REG_DATA_OFFSET         0x08
/* QDRH */
#define REG_DATA_HI_OFFSET      0x0A


/* Bank 18 */

/* IER */
#define REG_INT_MASK_BANK       18
#define REG_INT_MASK_OFFSET     0x00

#define INT_RX_ERROR            0x0080
#define INT_RX_STOPPED          0x0100
#define INT_TX_STOPPED          0x0200
#define INT_RX_EARLY            0x0400
#define INT_RX_OVERRUN          0x0800
#define INT_TX_UNDERRUN         0x1000
#define INT_RX                  0x2000
#define INT_TX                  0x4000
#define INT_PHY                 0x8000
#define INT_MASK                ( INT_RX | INT_TX )


/* ISR */
#define REG_INT_STATUS_BANK     18
#define REG_INT_STATUS_OFFSET   0x02

#ifdef SH_32BIT_ACCESS_ONLY
#define INT_STATUS( intr )  (( intr ) << 16 )
#endif

/* RXSR */
#define REG_RX_STATUS_BANK      18
#define REG_RX_STATUS_OFFSET    0x04

#define RX_BAD_CRC              0x0001
#define RX_TOO_SHORT            0x0002
#define RX_TOO_LONG             0x0004
#define RX_FRAME_ETHER          0x0008
#define RX_PHY_ERROR            0x0010
#define RX_UNICAST              0x0020
#define RX_MULTICAST            0x0040
#define RX_BROADCAST            0x0080
#define RX_SRC_PORTS            0x0F00
#define RX_VALID                0x8000
#define RX_ERRORS     ( RX_BAD_CRC | RX_TOO_LONG | RX_TOO_SHORT | RX_PHY_ERROR )


#define RX_SRC_PORTS_SHIFT      8

/* RXBC */
#define REG_RX_BYTE_CNT_BANK    18
#define REG_RX_BYTE_CNT_OFFSET  0x06

#define RX_BYTE_CNT_MASK        0x07FF

/* ETXR */
#define REG_EARLY_TX_BANK       18
#define REG_EARLY_TX_OFFSET     0x08

#define EARLY_TX_THRESHOLD      0x001F
#define EARLY_TX_ENABLE         0x0080
#define EARLY_TX_MULTIPLE       64

/* ERXR */
#define REG_EARLY_RX_BANK       18
#define REG_EARLY_RX_OFFSET     0x0A

#define EARLY_RX_THRESHOLD      0x001F
#define EARLY_RX_ENABLE         0x0080
#define EARLY_RX_MULTIPLE       64


/* Bank 19 */

#define REG_MULTICAST_BANK      19
/* MTR0 */
#define REG_MULTICAST_0_OFFSET  0x00
#define REG_MULTICAST_1_OFFSET  0x01
/* MTR1 */
#define REG_MULTICAST_2_OFFSET  0x02
#define REG_MULTICAST_3_OFFSET  0x03
/* MTR2 */
#define REG_MULTICAST_4_OFFSET  0x04
#define REG_MULTICAST_5_OFFSET  0x05
/* MTR3 */
#define REG_MULTICAST_6_OFFSET  0x06
#define REG_MULTICAST_7_OFFSET  0x07


#define REG_POWER_CNTL_BANK     19
/* PMCS */
#define REG_POWER_CNTL_OFFSET   0x08


#endif /* ifdef KS_ISA_BUS */

/*
 * KS8841/KS8842 interface to Host by PCI bus.
 */

#ifdef KS_PCI_BUS

/*
 * PCI Configuration ( Space ) Registers
 *
 */

#define CFID                    0x00               /* Configuration ID Register */
#define   CFID_DEVID              0xFFFF0000           /* vendor id, 2 bytes */
#define   CFID_VENID              0x0000FFFF           /* device id, 2 bytes */

#define CFCS                    0x04               /* Command and Status Configuration Register */
#define   CFCS_STAT               0xFFFF0000           /* status register, 2 bytes */
#define   CFCS_COMM               0x0000FFFF           /* command register, 2 bytes */
#define   CFCS_COMM_MEM           0x00000002           /* memory access enable */
#define   CFCS_COMM_MASTER        0x00000004           /* master enable */
#define   CFCS_COMM_PERRSP        0x00000040           /* parity error response */
#define   CFCS_COMM_SYSERREN      0x00000100           /* system error enable */
#define   COMM_SETTING           (CFCS_COMM_MEM | CFCS_COMM_MASTER | CFCS_COMM_PERRSP | CFCS_COMM_SYSERREN)

#define   CFCS_STAT_DPR           0x0100               /* Data Parity Error */
#define   CFCS_STAT_DST           0x0600               /* Device Select Timing */
#define   CFCS_STAT_RVTAB         0x1000               /* Received Target Abort */
#define   CFCS_STAT_RVMAB         0x2000               /* Received Master Abort */
#define   CFCS_STAT_SYSERR        0x4000               /* Signal System Error */
#define   CFCS_STAT_DPERR         0x8000               /* Detected Parity Error */


#define CFRV                    0x08               /* Configuration Revision Register */
#define   CFRV_BASCLASS           0xFF000000           /* basic code, 1 byte */
#define   CFRV_SUBCLASS           0x00FF0000           /* sub-class code, 1 byte */
#define   CFRV_REVID              0x000000FF           /* revision id (Revision\Step number), 1 byte */

#define CFLT                    0x0C               /* Configuration Latency Timer Register */
#define   CFLT_LATENCY_TIMER      0x0000FF00           /* latency timer, 1 byte */
#define   CFLT_CACHE_LINESZ       0x000000FF           /* cache line size, 1 byte */
#define   LATENCY_TIMER           0x00000080           /* default latency timer - 0 */
#define   CACHE_LINESZ                     8           /* default cache line size - 8 (8-DWORD) */

#define CMBA                    0x10               /* Configuration Memory Base Address Register */

#define CSID                    0x2C               /* Subsystem ID Register */
#define   CSID_SUBSYSID           0xFFFF0000           /* Subsystem ID, 2 bytes */
#define   CSID_SUBVENID           0x0000FFFF           /* Subsystem Vendor ID, 2 bytes*/

#define CFIT                    0x3C               /* Configuration Interrupt Register */
#define   CFIT_MAX_L              0xFF000000           /* maximum latency, 1 byte */
#define   CFIT_MIN_G              0x00FF0000           /* minimum grant, 1 byte */
#define   CFIT_IPIN               0x0000FF00           /* interrupt pin, 1 byte */
#define   CFIT_ILINE              0x000000FF           /* interrupt line, 1 byte */
#define   MAX_LATENCY                   0x28           /* default maximum latency - 0x28 */
#define   MIN_GRANT                     0x14           /* default minimum grant - 0x14 */

#define CPMC                    0x54               /* Power Management Control and Status Register */


/* DMA Registers */

#define REG_DMA_TX_CTRL             0x0000
#define DMA_TX_CTRL_ENABLE          0x00000001
#define DMA_TX_CTRL_CRC_ENABLE      0x00000002
#define DMA_TX_CTRL_PAD_ENABLE      0x00000004
#define DMA_TX_CTRL_LOOPBACK        0x00000100
#define DMA_TX_CTRL_FLOW_ENABLE     0x00000200
#define DMA_TX_CTRL_CSUM_IP         0x00010000
#define DMA_TX_CTRL_CSUM_TCP        0x00020000
#define DMA_TX_CTRL_CSUM_UDP        0x00040000
#define DMA_TX_CTRL_BURST_SIZE      0x3F000000

#define REG_DMA_RX_CTRL             0x0004
#define DMA_RX_CTRL_ENABLE          0x00000001
#define DMA_RX_CTRL_MULTICAST       0x00000002
#define DMA_RX_CTRL_PROMISCUOUS     0x00000004
#define DMA_RX_CTRL_ERROR           0x00000008
#define DMA_RX_CTRL_UNICAST         0x00000010
#define DMA_RX_CTRL_ALL_MULTICAST   0x00000020
#define DMA_RX_CTRL_BROADCAST       0x00000040
#define DMA_RX_CTRL_FLOW_ENABLE     0x00000200
#define DMA_RX_CTRL_CSUM_IP         0x00010000
#define DMA_RX_CTRL_CSUM_TCP        0x00020000
#define DMA_RX_CTRL_CSUM_UDP        0x00040000
#define DMA_RX_CTRL_BURST_SIZE      0x3F000000

#define REG_DMA_TX_START            0x0008
#define REG_DMA_RX_START            0x000C
#define DMA_START                   0x00000001      /* DMA start command */

#define REG_DMA_TX_ADDR             0x0010
#define REG_DMA_RX_ADDR             0x0014

#define DMA_ADDR_LIST_MASK          0xFFFFFFFC
#define DMA_ADDR_LIST_SHIFT         2

/* MTR0 */
#define REG_MULTICAST_0_OFFSET      0x0020
#define REG_MULTICAST_1_OFFSET      0x0021
#define REG_MULTICAST_2_OFFSET      0x0022
#define REG_MULTICAST_3_OFFSET      0x0023
/* MTR1 */
#define REG_MULTICAST_4_OFFSET      0x0024
#define REG_MULTICAST_5_OFFSET      0x0025
#define REG_MULTICAST_6_OFFSET      0x0026
#define REG_MULTICAST_7_OFFSET      0x0027

/* Interrupt Registers */

/* INTEN */
#define REG_INTERRUPTS_ENABLE       0x0028
/* INTST */
#define REG_INTERRUPTS_STATUS       0x002C

#define INT_WAN_RX_STOPPED          0x02000000
#define INT_WAN_TX_STOPPED          0x04000000
#define INT_WAN_RX_BUF_UNAVAIL      0x08000000