📄 hardware.h
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typedef struct
{
TDescStat Control;
TDescBuf BufSize;
ULONG ulBufAddr;
ULONG ulNextPtr;
} THw_Desc, *PTHw_Desc;
typedef struct
{
TDescStat Control;
TDescBuf BufSize;
/* Current buffers size value in hardware descriptor. */
ULONG ulBufSize;
} TSw_Desc, *PTSw_Desc;
typedef struct _Desc
{
/* Hardware descriptor pointer to uncached physical memory. */
PTHw_Desc phw;
/* Cached memory to hold hardware descriptor values for manipulation. */
TSw_Desc sw;
/* Operating system dependent data structure to hold physical memory buffer
allocation information.
*/
PVOID pReserved;
#ifdef CHECK_OVERRUN
PTHw_Desc pCheck;
#endif
} TDesc, *PTDesc;
typedef struct
{
/* First descriptor in the ring. */
PTDesc pRing;
/* Current descriptor being manipulated. */
PTDesc pCurrent;
/* First hardware descriptor in the ring. */
PTHw_Desc phwRing;
/* The physical address of the first descriptor of the ring. */
ULONG ulRing;
int nSize;
/* Number of descriptors allocated. */
int cnAlloc;
/* Number of descriptors available for use. */
int cnAvail;
/* Index for last descriptor released to hardware .*/
int iLast;
/* Index for next descriptor available for use. */
int iNext;
/* Mask for index wrapping. */
int iMax;
} TDescInfo, *PTDescInfo;
#endif
/* DMA Transfer structure */
typedef struct _DMA_TX
{
ULONG dma_len; /* Tx data length by DMA */
void *dma_txBuf; /* Tx buffer to free after DMA transmit transfer done */
} DMA_TX, *PDMA_TX;
typedef struct _DMA_RX
{
ULONG dma_len; /* Rx data length by DMA */
void *dma_rxBuf; /* Rx buffer pass to uplayer after DMA receive transfer done */
} DMA_RX, *PDMA_RX;
typedef struct _DMA_XFER
{
BOOLEAN f_dma_rx; /* TRUE, using DMA to move packet data from device to host memory */
BOOLEAN f_dma_tx; /* TRUE, using DMA to move packet data from host memory to device */
ULONG dma_threshold; /* specifies the minimum size a packet must be for using DMA */
UCHAR dma_rx_channel; /* specifies the DMA channel to use for receiving packets */
UCHAR dma_tx_channel; /* specifies the DMA channel to use for transmitting packets */
ULONG dma_align_mask; /* specifies the DMA transfer address alignment mask */
DMA_TX dma_tx; /* DMA Tx buffer information */
DMA_RX dma_rx; /* DMA Rx buffer information */
} DMA_XFER, *PDMA_XFER;
struct hw_fn;
typedef struct
{
struct hw_fn* m_hwfn;
UCHAR m_bPermanentAddress[ MAC_ADDRESS_LENGTH ];
UCHAR m_bOverrideAddress[ MAC_ADDRESS_LENGTH ];
/* PHY status info. */
ULONG m_ulHardwareState;
ULONG m_ulTransmitRate;
ULONG m_ulDuplex;
/* hardware resources */
PUCHAR m_pVirtualMemory;
ULONG m_ulVIoAddr; /* device's base address */
ULONG m_boardBusEndianMode; /* board bus endian mode board specific */
UCHAR m_bMacOverrideAddr;
UCHAR m_bBroadcastPercent;
USHORT m_w802_1P_Mapping;
USHORT m_wDiffServ[ 64 ]; /* possible values from 6-bit of ToS (bit7 ~ bit2) field */
USHORT m_b802_1P_Priority[8]; /* possible values from 3-bit of 802.1p Tag priority field */
MAC_TABLE m_MacTable[ STATIC_MAC_TABLE_ENTRIES ];
PORT_CONFIG m_Port[ TOTAL_PORT_NUM ]; /* Device switch MIB counters */
PORT_INFO m_PortInfo[ SWITCH_PORT_NUM ];
VLAN_TABLE m_VlanTable[ VLAN_TABLE_ENTRIES ];
#ifdef KS_PCI_BUS
ULONG m_dwTransmitConfig;
ULONG m_dwReceiveConfig;
USHORT m_wTransmitThreshold;
USHORT m_wReceiveThreshold;
ULONG m_ulInterruptMask;
ULONG m_ulInterruptSet;
UCHAR m_bReceiveStop;
#else
USHORT m_wTransmitConfig;
USHORT m_wTransmitThreshold;
USHORT m_wReceiveConfig;
USHORT m_wReceiveThreshold;
USHORT m_wInterruptMask;
UCHAR m_bBurstLength;
UCHAR m_bReserved1;
#endif
UCHAR m_bEnabled;
UCHAR m_bPromiscuous;
UCHAR m_bAllMulticast;
/* List of multicast addresses in use. */
UCHAR m_bMulticastListSize;
UCHAR m_bMulticastList[ MAX_MULTICAST_LIST ]
[ MAC_ADDRESS_LENGTH ];
/* member variables used for receiving */
#ifdef KS_PCI_BUS
PUCHAR m_bLookahead;
#else
UCHAR m_bLookahead[ MAX_BUF_SIZE ];
#endif
int m_nPacketLen;
/* member variables used for sending commands, mostly for debug purpose */
int m_nWaitDelay[ WAIT_DELAY_LAST ];
/* member variables for statistics */
ULONGLONG m_cnCounter[ SWITCH_PORT_NUM ][ OID_COUNTER_LAST ]; /* Driver statistics counter */
ULONG m_nBad[ COUNT_BAD_LAST ];
ULONG m_nGood[ COUNT_GOOD_LAST ];
UCHAR m_bBank;
UCHAR m_bReceiveDiscard;
UCHAR m_bSentPacket;
UCHAR m_bTransmitPacket;
/* hardware configurations read from the registry */
UCHAR m_bDuplex; /* 10: 10BT; 100: 100BT */
UCHAR m_bSpeed; /* 1: Full duplex; 2: half duplex */
USHORT m_wPhyAddr;
UCHAR m_bMulticastBits[ HW_MULTICAST_SIZE ];
UCHAR f_dircetMode; /* 1: Tx by direct mode, 0:Tx by loopkup mode */
UCHAR m_bReserved2[ 3 ];
UCHAR m_bPort;
UCHAR m_bPortAlloc;
UCHAR m_bPortRX; /* 1:Rx from Port1; 2:Rx from Port2 */
UCHAR m_bPortTX; /* 1:Tx to Port1; 2:Tx to Port2; 3:Tx to Port1 and Port2; 0:Tx by loopkup mode */
UCHAR m_fPortTX;
UCHAR m_bStarted;
UCHAR m_bAcquire;
UCHAR m_bPortSelect;
/* member variables used for saving registers during interrupt */
UCHAR m_bSavedBank;
UCHAR m_bSavedPacket;
USHORT m_wSavedPointer;
#ifdef KS_PCI_BUS
TDescInfo m_RxDescInfo;
TDescInfo m_TxDescInfo;
#ifdef SKIP_TX_INT
int m_TxIntCnt;
int m_TxIntMask;
#endif
void* m_pPciCfg;
#ifdef DEBUG_OVERRUN
ULONG m_ulDropped;
ULONG m_ulReceived;
#endif
#endif
void* m_pDevice;
#ifdef KS_ISA_BUS
#ifdef UNDER_CE
UCHAR reg[ 54 ][ 16 ];
#endif
#endif
/* member variables used for DMA function */
DMA_XFER dmaInfo;
/* for debug hardware transmit\receive packets */
UCHAR fDebugDumpTx; /* Dump transmit packets to Consult port */
UCHAR fDebugDumpRx; /* Dump received packets to Consult port */
UCHAR fLoopbackStart; /* loopback the received packets to trasnmit. */
UCHAR m_bReserved3;
} HARDWARE, *PHARDWARE;
struct hw_fn {
int m_fPCI;
void ( *fnSwitchDisableMirrorSniffer )( PHARDWARE, UCHAR );
void ( *fnSwitchEnableMirrorSniffer )( PHARDWARE, UCHAR );
void ( *fnSwitchDisableMirrorReceive )( PHARDWARE, UCHAR );
void ( *fnSwitchEnableMirrorReceive )( PHARDWARE, UCHAR );
void ( *fnSwitchDisableMirrorTransmit )( PHARDWARE, UCHAR );
void ( *fnSwitchEnableMirrorTransmit )( PHARDWARE, UCHAR );
void ( *fnSwitchDisableMirrorRxAndTx )( PHARDWARE );
void ( *fnSwitchEnableMirrorRxAndTx )( PHARDWARE );
void ( *fnHardwareConfig_TOS_Priority )( PHARDWARE, UCHAR, USHORT );
void ( *fnSwitchDisableDiffServ )( PHARDWARE, UCHAR );
void ( *fnSwitchEnableDiffServ )( PHARDWARE, UCHAR );
void ( *fnHardwareConfig802_1P_Priority )( PHARDWARE, UCHAR, USHORT );
void ( *fnSwitchDisable802_1P )( PHARDWARE, UCHAR );
void ( *fnSwitchEnable802_1P )( PHARDWARE, UCHAR );
void ( *fnSwitchDisableDot1pRemapping )( PHARDWARE, UCHAR );
void ( *fnSwitchEnableDot1pRemapping )( PHARDWARE, UCHAR );
void ( *fnSwitchConfigPortBased )( PHARDWARE, UCHAR, UCHAR );
void ( *fnSwitchDisableMultiQueue )( PHARDWARE, UCHAR );
void ( *fnSwitchEnableMultiQueue )( PHARDWARE, UCHAR );
void ( *fnSwitchDisableBroadcastStorm )( PHARDWARE, UCHAR );
void ( *fnSwitchEnableBroadcastStorm )( PHARDWARE, UCHAR );
void ( *fnHardwareConfigBroadcastStorm )( PHARDWARE, UCHAR );
void ( *fnSwitchDisablePriorityRate )( PHARDWARE, UCHAR );
void ( *fnSwitchEnablePriorityRate )( PHARDWARE, UCHAR );
void ( *fnHardwareConfigRxPriorityRate )( PHARDWARE, UCHAR, UCHAR,
ULONG );
void ( *fnHardwareConfigTxPriorityRate )( PHARDWARE, UCHAR, UCHAR,
ULONG );
void ( *fnPortSet_STP_State )( PHARDWARE, UCHAR, int );
void ( *fnPortReadMIBCounter )( PHARDWARE, UCHAR, USHORT, PULONGLONG );
void ( *fnPortReadMIBPacket )( PHARDWARE, UCHAR, PULONG, PULONGLONG );
void ( *fnSwitchEnableVlan )( PHARDWARE );
};
#ifdef NDIS_MINIPORT_DRIVER
#if defined( NDIS50_MINIPORT ) || defined( NDIS51_MINIPORT )
#include <poppack.h>
#else
#ifdef UNDER_CE
#pragma warning(disable:4103)
#pragma pack(1)
#else
#include <packoff.h>
#endif
#endif
#endif
#define BASE_IO_RANGE 0x10
#if 1
#define AUTO_RELEASE
#endif
#if 1
#define AUTO_FAST_AGING
#endif
#if 0
#define EARLY_RECEIVE
#endif
#if 0
#define EARLY_TRANSMIT
#endif
/* Bank select register offset is accessible in all banks to allow bank
selection.
*/
#define REG_BANK_SEL_OFFSET 0x0E
/* -------------------------------------------------------------------------- */
/*
KS8841\KS8842 register definitions
*/
#define SW_PHY_AUTO 0 /* autosense */
#define SW_PHY_10BASE_T 1 /* 10Base-T */
#define SW_PHY_10BASE_T_FD 2 /* 10Base-T Full Duplex */
#define SW_PHY_100BASE_TX 3 /* 100Base-TX */
#define SW_PHY_100BASE_TX_FD 4 /* 100Base-TX Full Duplex */
/* Default setting definitions */
#define KS8695_MIN_FBUF (1536) /* min data buffer size */
#define BUFFER_1568 1568 /* 0x620 */
#define BUFFER_2044 2044 /* 2K-4 buffer to meet Huge packet support (1916 bytes)
(max buffer length that ks884x allowed */
#define RXCHECKSUM_DEFAULT TRUE /* HW Rx IP/TCP/UDP checksum enable */
#define TXCHECKSUM_DEFAULT TRUE /* HW Tx IP/TCP/UDP checksum enable */
#define FLOWCONTROL_DEFAULT TRUE /* Flow control enable */
#define PBL_DEFAULT 8 /* DMA Tx/Rx burst Size. 0:unlimited, other value for (4 * x) */
#define PHY_POWERDOWN_DEFAULT TRUE /* PHY PowerDown Reset enable */
#define PHY_SPEED_DEFAULT SW_PHY_AUTO /* PHY auto-negotiation enable */
#define PORT_STP_DEFAULT FALSE /* Spanning tree disable */
#define PORT_STORM_DEFAULT TRUE /* Broadcast storm protection enable */
/* OBCR */
#define BUS_SPEED_125_MHZ 0x0000
#define BUS_SPEED_62_5_MHZ 0x0001
#define BUS_SPEED_41_66_MHZ 0x0002
#define BUS_SPEED_25_MHZ 0x0003
/* EEPCR */
#define EEPROM_CHIP_SELECT 0x0001
#define EEPROM_SERIAL_CLOCK 0x0002
#define EEPROM_DATA_OUT 0x0004
#define EEPROM_DATA_IN 0x0008
#define EEPROM_ACCESS_ENABLE 0x0010
/* MBIR */
#define RX_MEM_TEST_FAILED 0x0008
#define RX_MEM_TEST_FINISHED 0x0010
#define TX_MEM_TEST_FAILED 0x0800
#define TX_MEM_TEST_FINISHED 0x1000
/* PMCS */
#define POWER_STATE_D0 0x0000
#define POWER_STATE_D1 0x0001
#define POWER_STATE_D2 0x0002
#define POWER_STATE_D3 0x0003
#define POWER_STATE_MASK 0x0003
#define POWER_PME_ENABLE 0x0100
#define POWER_PME_STATUS 0x8000
/* WFCR */
#define WOL_MAGIC_ENABLE 0x0080
#define WOL_FRAME3_ENABLE 0x0008
#define WOL_FRAME2_ENABLE 0x0004
#define WOL_FRAME1_ENABLE 0x0002
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