hardware.h

MICREL 网卡驱动 FOR CE 5.0

/* ---------------------------------------------------------------------------
          Copyright (c) 2003-2006 Micrel, Inc.  All rights reserved.
   ---------------------------------------------------------------------------

    hardware.h - Target independent hardware header

    Author  Date      Version  Description
    PCD     07/13/06  1.1.0    Add support using DAM to transfer packet data
                               between host memory and KSZ88xxM QMU.
    THa     06/29/06  1.0.4    Add 1912 bytes large frame support.
    THa     06/07/06           Hardware interrupts may not be disabled
                               immediately after the register is written to.
    THa     04/06/06           Implement AT93C46 EEPROM access functions.
    THa     02/28/06           Do not use HW_WRITE_BYTE because of limitation of
                               some hardware platforms.
    THa     01/25/06           Add HardwareWriteIntMask and
                               HardwareWriteIntStat functions for 32-bit I/O
                               access only.
    THa     01/13/06           Transfer dword-aligned data for performance.
    THa     10/06/05           Changed descriptor structure.
    THa     08/15/05           Added PCI configuration I/O.
    PCD     03/30/05  0.1.0    First release.
                               (1). CLI read\write device registers works.
                               (2). Driver Initialization device works .
                               (3). Driver Interrupt Server Routine works.
                               (4). Driver transmit packets to device port works.
                               (5). Driver receive packsts from device works.
    THa     02/23/04           Use inline functions to improve performance.
    THa     10/05/04           Updated for PCI version.
    THa     10/14/04           Updated with latest specs.
    THa     12/10/03  0.0.1    Created file.
   ---------------------------------------------------------------------------
*/


#ifndef __HARDWARE_H
#define __HARDWARE_H

#include "target.h"


#ifdef DBG
#ifndef UNDER_CE
#define DEBUG_COUNTER
#define DEBUG_TIMEOUT
#endif

#if 0
#define DEBUG_INTERRUPT
#endif
#if 0
#define DEBUG_MEM
#endif
#if 0
#define DEBUG_RX
#endif
#if 0
#define DEBUG_RX_DATA
#endif
#if 0
#define DEBUG_TX
#endif
#if 0
#define DEBUG_RX_DESC
#endif
#if 0
#define DEBUG_RX_DESC_CHECK
#endif
#if 0
#define DEBUG_TX_DESC
#endif
#if 0
#define DEBUG_TX_DESC_CHECK
#endif
#endif

#if 0
#define INLINE
#endif
#if 0
#define RCV_HUGE_FRAME
#endif

#ifdef KS_PCI_BUS
#if 0
#define CHECK_RCV_ERRORS
#endif
#if 1
#define SKIP_TX_INT
#endif
#endif


/* define it if software support STP protocol */
#undef SOFTWARE_STP_SUPPORT


/* -------------------------------------------------------------------------- */

#define MAC_ADDRESS_LENGTH  6

/* -------------------------------------------------------------------------- */

#ifdef NDIS_MINIPORT_DRIVER
#if defined( NDIS50_MINIPORT )  ||  defined( NDIS51_MINIPORT )
#include <pshpack1.h>

#else
#include <packon.h>
#endif
#endif

#include "ks_def.h"

/* define max switch port */
#ifdef DEF_KS8842
#define MAX_SWITCH_PORT   2
#else
#define MAX_SWITCH_PORT   1
#endif

#define MAX_ETHERNET_BODY_SIZE  1500
#define ETHERNET_HEADER_SIZE    14

#define MAXIMUM_ETHERNET_PACKET_SIZE  \
    ( MAX_ETHERNET_BODY_SIZE + ETHERNET_HEADER_SIZE )

#define MAX_BUF_SIZE            2048

#define TX_BUF_SIZE             2000
#define RX_BUF_SIZE             2000

#define NDIS_MAX_LOOKAHEAD      ( RX_BUF_SIZE - ETHERNET_HEADER_SIZE )

#define MAX_MULTICAST_LIST      32

#define HW_MULTICAST_SIZE       8


#define MAC_ADDR_ORDER( i )  ( MAC_ADDRESS_LENGTH - 1 - ( i ))


#define MAIN_PORT   0
#define OTHER_PORT  1
#define HOST_PORT   2

#define PORT_1      1
#define PORT_2      2

#define DEV_TO_HW_PORT( port )  ( port + 1 )
#define HW_TO_DEV_PORT( port )  ( port - 1 )

/* Driver set Switch broadcast storm protection at 10% rate */
#define BROADCAST_STORM_PROTECTION_RATE    10


typedef enum
{
    MediaStateConnected,
    MediaStateDisconnected
} MEDIA_STATE;


typedef enum
{
    OID_COUNTER_UNKOWN,

    OID_COUNTER_FIRST,
    OID_COUNTER_DIRECTED_BYTES_XMIT = OID_COUNTER_FIRST, /* total bytes transmitted  */
    OID_COUNTER_DIRECTED_FRAMES_XMIT,    /* total packets transmitted */

    OID_COUNTER_BROADCAST_BYTES_XMIT,
    OID_COUNTER_BROADCAST_FRAME_XMIT,

    OID_COUNTER_DIRECTED_BYTES_RCV,      /* total bytes received   */
    OID_COUNTER_DIRECTED_FRAMES_RCV,     /* total packets received */
    OID_COUNTER_BROADCAST_BYTES_RCV,
    OID_COUNTER_BROADCAST_FRAMES_RCV,    /* total broadcast packets received (RXSR: RXBF)                */
    OID_COUNTER_MULTICAST_FRAMES_RCV,    /* total multicast packets received (RXSR: RXMF) or (RDSE0: MF) */
    OID_COUNTER_UNICAST_FRAMES_RCV,      /* total unicast packets received   (RXSR: RXUF)                */

    OID_COUNTER_XMIT_ERROR,              /* total transmit errors */
    OID_COUNTER_XMIT_LATE_COLLISION,     /* transmit Late Collision (TXSR: TXLC) */
    OID_COUNTER_XMIT_MORE_COLLISIONS,    /* transmit Maximum Collision (TXSR: TXMC) */
    OID_COUNTER_XMIT_UNDERRUN,           /* transmit Underrun (TXSR: TXUR) */
    OID_COUNTER_XMIT_ALLOC_FAIL,         /* transmit fail because no enought memory in the Tx Packet Memory */
    OID_COUNTER_XMIT_DROPPED,            /* transmit packet drop because no buffer in the host memory */
    OID_COUNTER_XMIT_INT_UNDERRUN,       /* transmit underrun from interrupt status (ISR: TXUIS) */
    OID_COUNTER_XMIT_INT_STOP,           /* transmit DMA MAC process stop from interrupt status (ISR: TXPSIE) */
    OID_COUNTER_XMIT_INT,                /* transmit Tx interrupt status (ISR: TXIE) */

    OID_COUNTER_RCV_ERROR,               /* total receive errors */
    OID_COUNTER_RCV_ERROR_CRC,           /* receive packet with CRC error (RXSR: RXCE) or (RDSE0: CE) */
    OID_COUNTER_RCV_ERROR_MII,           /* receive MII error (RXSR: RXMR) or (RDSE0: RE) */
    OID_COUNTER_RCV_ERROR_TOOLONG,       /* receive frame too long error (RXSR: RXTL) or (RDSE0: TL)  */
    OID_COUNTER_RCV_ERROR_RUNT,          /* receive Runt frame error (RXSR: RXRF) or (RDSE0: RF)  */
    OID_COUNTER_RCV_INVALID_FRAME,       /* receive invalid frame (RXSR: RXFV) */
    OID_COUNTER_RCV_ERROR_IP,            /* receive frame with IP checksum error  (RDSE0: IPE) */
    OID_COUNTER_RCV_ERROR_TCP,           /* receive frame with TCP checksum error (RDSE0: TCPE) */
    OID_COUNTER_RCV_ERROR_UDP,           /* receive frame with UDP checksum error (RDSE0: UDPE) */
    OID_COUNTER_RCV_NO_BUFFER,           /* receive failed on memory allocation for the incoming frames from interrupt status (ISR: RXOIS). */
    OID_COUNTER_RCV_DROPPED,             /* receive packet drop because no buffer in the host memory */
    OID_COUNTER_RCV_INT_ERROR,           /* receive error from interrupt status (ISR: RXEFIE) */
    OID_COUNTER_RCV_INT_STOP,            /* receive DMA MAC process stop from interrupt status (ISR: RXPSIE) */
    OID_COUNTER_RCV_INT,                 /* receive Rx interrupt status (ISR: RXIE) */

    OID_COUNTER_XMIT_OK,
    OID_COUNTER_RCV_OK,

    OID_COUNTER_RCV_ERROR_LEN,

    OID_COUNTER_LAST
} EOidCounter;


enum
{
    COUNT_BAD_FIRST,
    COUNT_BAD_ALLOC = COUNT_BAD_FIRST,
    COUNT_BAD_CMD,
    COUNT_BAD_CMD_BUSY,
    COUNT_BAD_CMD_INITIALIZE,
    COUNT_BAD_CMD_MEM_ALLOC,
    COUNT_BAD_CMD_RESET,
    COUNT_BAD_CMD_WRONG_CHIP,
    COUNT_BAD_COPY_DOWN,
    COUNT_BAD_RCV_FRAME,
    COUNT_BAD_RCV_PACKET,
    COUNT_BAD_SEND,
    COUNT_BAD_SEND_DIFF,
    COUNT_BAD_SEND_PACKET,
    COUNT_BAD_SEND_ZERO,
    COUNT_BAD_XFER_ZERO,
    COUNT_BAD_LAST
};


enum
{
    COUNT_GOOD_FIRST,
    COUNT_GOOD_CMD_RESET = COUNT_GOOD_FIRST,
    COUNT_GOOD_CMD_RESET_MMU,
    COUNT_GOOD_COPY_DOWN_ODD,
    COUNT_GOOD_INT,
    COUNT_GOOD_INT_LOOP,
    COUNT_GOOD_INT_ALLOC,
    COUNT_GOOD_INT_RX,
    COUNT_GOOD_INT_RX_EARLY,
    COUNT_GOOD_INT_RX_OVERRUN,
    COUNT_GOOD_INT_TX,
    COUNT_GOOD_INT_TX_EMPTY,
    COUNT_GOOD_NEXT_PACKET,
    COUNT_GOOD_NO_NEXT_PACKET,
    COUNT_GOOD_RCV_COMPLETE,
    COUNT_GOOD_RCV_DISCARD,
    COUNT_GOOD_RCV_NOT_DISCARD,
    COUNT_GOOD_SEND_PACKET,
    COUNT_GOOD_SEND_QUEUE,
    COUNT_GOOD_SEND_ZERO,
    COUNT_GOOD_XFER_ZERO,
    COUNT_GOOD_LAST
};


enum
{
    WAIT_DELAY_FIRST,
    WAIT_DELAY_PHY_RESET = WAIT_DELAY_FIRST,
    WAIT_DELAY_AUTO_NEG,
    WAIT_DELAY_MEM_ALLOC,
    WAIT_DELAY_CMD_BUSY,
    WAIT_DELAY_LAST
};


#ifdef KS_PCI_BUS

#if 0
#define CHECK_OVERRUN
#endif
#ifdef DBG
#if 1
#define DEBUG_OVERRUN
#endif
#endif


#define DESC_ALIGNMENT              16
#define BUFFER_ALIGNMENT            8


#define NUM_OF_RX_DESC  128
#define NUM_OF_TX_DESC  32

#define DESC_RX_FRAME_LEN        0x000007FF
#define DESC_RX_FRAME_TYPE       0x00008000
#define DESC_RX_ERROR_CRC        0x00010000
#define DESC_RX_ERROR_RUNT       0x00020000
#define DESC_RX_ERROR_TOO_LONG   0x00040000
#define DESC_RX_ERROR_PHY        0x00080000
#define DESC_RX_PORT_MASK        0x00300000
#define DESC_RX_MULTICAST        0x01000000
#define DESC_RX_ERROR            0x02000000
#define DESC_RX_ERROR_CSUM_UDP   0x04000000
#define DESC_RX_ERROR_CSUM_TCP   0x08000000
#define DESC_RX_ERROR_CSUM_IP    0x10000000
#define DESC_RX_LAST             0x20000000
#define DESC_RX_FIRST            0x40000000

#define DESC_HW_OWNED            0x80000000

#define DESC_BUF_SIZE            0x000007FF
#define DESC_TX_PORT_MASK        0x00300000
#define DESC_END_OF_RING         0x02000000
#define DESC_TX_CSUM_GEN_UDP     0x04000000
#define DESC_TX_CSUM_GEN_TCP     0x08000000
#define DESC_TX_CSUM_GEN_IP      0x10000000
#define DESC_TX_LAST             0x20000000
#define DESC_TX_FIRST            0x40000000
#define DESC_TX_INTERRUPT        0x80000000

#define DESC_RX_MASK  ( DESC_BUF_SIZE )

#define DESC_TX_MASK  ( DESC_TX_INTERRUPT | DESC_TX_FIRST | DESC_TX_LAST | \
    DESC_BUF_SIZE )


typedef struct
{
    ULONG wFrameLen     : 11;
    ULONG ulReserved1   : 4;
    ULONG fFrameType    : 1;
    ULONG fErrCRC       : 1;
    ULONG fErrRunt      : 1;
    ULONG fErrTooLong   : 1;
    ULONG fErrPHY       : 1;
    ULONG ulSourePort   : 4;
    ULONG fMulticast    : 1;
    ULONG fError        : 1;
    ULONG fCsumErrUDP   : 1;
    ULONG fCsumErrTCP   : 1;
    ULONG fCsumErrIP    : 1;
    ULONG fLastDesc     : 1;
    ULONG fFirstDesc    : 1;
    ULONG fHWOwned      : 1;
} TDescRxStat;

typedef struct
{
    ULONG ulReserved1   : 31;
    ULONG fHWOwned      : 1;
} TDescTxStat;

typedef struct
{
    ULONG wBufSize      : 11;
    ULONG ulReserved3   : 14;
    ULONG fEndOfRing    : 1;
    ULONG ulReserved4   : 6;
} TDescRxBuf;

typedef struct
{
    ULONG wBufSize      : 11;
    ULONG ulReserved3   : 9;
    ULONG ulDestPort    : 4;
    ULONG ulReserved4   : 1;
    ULONG fEndOfRing    : 1;
    ULONG fCsumGenUDP   : 1;
    ULONG fCsumGenTCP   : 1;
    ULONG fCsumGenIP    : 1;
    ULONG fLastSeg      : 1;
    ULONG fFirstSeg     : 1;
    ULONG fInterrupt    : 1;
} TDescTxBuf;

typedef union
{
    TDescRxStat rx;
    TDescTxStat tx;
    ULONG       ulData;
} TDescStat;

typedef union
{
    TDescRxBuf rx;
    TDescTxBuf tx;
    ULONG      ulData;
} TDescBuf;