ks_def.h

MICREL 网卡驱动 FOR CE 5.0

#define REG_P2CR2_BANK              REG_PORT_2_CTRL_BANK
#define REG_P2CR2_OFFSET            0x02

#define REG_P2VIDCR_BANK            REG_PORT_2_CTRL_BANK
#define REG_P2VIDCR_OFFSET          0x04

#define REG_P2CR3_BANK              REG_PORT_2_CTRL_BANK
#define REG_P2CR3_OFFSET            0x06

#define REG_P2IRCR_BANK             REG_PORT_2_CTRL_BANK
#define REG_P2IRCR_OFFSET           0x08

#define REG_P2ERCR_BANK             REG_PORT_2_CTRL_BANK
#define REG_P2ERCR_OFFSET           0x0A

#define REG_P2SCSLMD_BANK           REG_PORT_2_LINK_CTRL_BANK
#define REG_P2SCSLMD_OFFSET         0x00

#define REG_P2CR4_BANK              REG_PORT_2_LINK_CTRL_BANK
#define REG_P2CR4_OFFSET            0x02

#define REG_P2SR_BANK               REG_PORT_1_LINK_CTRL_BANK
#define REG_P2SR_OFFSET             0x04

#define REG_P3CR1_BANK              REG_PORT_3_CTRL_BANK
#define REG_P3CR1_OFFSET            0x02

#define REG_P3CR2_BANK              REG_PORT_3_CTRL_BANK
#define REG_P3CR2_OFFSET            0x02

#define REG_P3VIDCR_BANK            REG_PORT_3_CTRL_BANK
#define REG_P3VIDCR_OFFSET          0x04

#define REG_P3CR3_BANK              REG_PORT_3_CTRL_BANK
#define REG_P3CR3_OFFSET            0x06

#define REG_P3IRCR_BANK             REG_PORT_3_CTRL_BANK
#define REG_P3IRCR_OFFSET           0x08

#define REG_P3ERCR_BANK             REG_PORT_3_CTRL_BANK
#define REG_P3ERCR_OFFSET           0x0A

#define REG_P3SCSLMD_BANK           REG_PORT_3_LINK_CTRL_BANK
#define REG_P3SCSLMD_OFFSET         0x00

#define REG_P3CR4_BANK              REG_PORT_3_LINK_CTRL_BANK
#define REG_P3CR4_OFFSET            0x02

#define REG_P3SR_BANK               REG_PORT_1_LINK_CTRL_BANK
#define REG_P3SR_OFFSET             0x04

#define REG_PORT_CTRL_1_OFFSET      0x00

#define REG_PORT_CTRL_2_OFFSET      0x02
#define REG_PORT_CTRL_2_HI_OFFSET   0x03

#define REG_PORT_CTRL_VID_OFFSET    0x04

#define REG_PORT_CTRL_3_OFFSET      0x06

#define REG_PORT_IN_RATE_OFFSET     0x08
#define REG_PORT_OUT_RATE_OFFSET    0x0A

#define REG_PORT_LINK_MD_RESULT     0x00
#define REG_PORT_LINK_MD_CTRL       0x01

#define REG_PORT_CTRL_4_OFFSET      0x02

#define REG_PORT_STATUS_OFFSET      0x04
#define REG_PORT_STATUS_HI_OFFSET   0x05
#endif

/* -------------------------------------------------------------------------- */

/* KS884X PCI registers */

#ifdef KS_PCI_BUS
#define REG_SIDER_PCI               0x0400

#define REG_CHIP_ID_OFFSET          REG_SIDER_PCI
#define REG_FAMILY_ID_OFFSET        ( REG_CHIP_ID_OFFSET + 1 )

#define REG_SGCR1_PCI               0x0402

#define REG_SWITCH_CTRL_1_OFFSET    REG_SGCR1_PCI
#define REG_SWITCH_CTRL_1_HI_OFFSET ( REG_SWITCH_CTRL_1_OFFSET + 1 )

#define REG_SGCR2_PCI               0x0404

#define REG_SWITCH_CTRL_2_OFFSET    REG_SGCR2_PCI
#define REG_SWITCH_CTRL_2_HI_OFFSET ( REG_SWITCH_CTRL_2_OFFSET + 1 )

#define REG_SGCR3_PCI               0x0406
#define REG_SGCR3_OFFSET            REG_SGCR3_PCI

#define REG_SWITCH_CTRL_3_OFFSET    REG_SGCR3_PCI
#define REG_SWITCH_CTRL_3_HI_OFFSET ( REG_SWITCH_CTRL_3_OFFSET + 1 )

#define REG_SGCR4_PCI               0x0408
#define REG_SGCR5_PCI               0x040A

#define REG_SGCR6_PCI               0x0410

#define REG_SWITCH_CTRL_6_OFFSET    REG_SGCR6_PCI


#define REG_PHAR_PCI                0x0420
#define REG_LBS21R_PCI              0x0424
#define REG_LBRCTCER_PCI            0x0426


#define REG_MACAR1_PCI              0x0470
#define REG_MACAR2_PCI              0x0472
#define REG_MACAR3_PCI              0x0474

#define REG_MAC_ADDR_0_OFFSET       REG_MACAR1_PCI
#define REG_MAC_ADDR_1_OFFSET       ( REG_MAC_ADDR_0_OFFSET + 1 )
#define REG_MAC_ADDR_2_OFFSET       REG_MACAR2_PCI
#define REG_MAC_ADDR_3_OFFSET       ( REG_MAC_ADDR_2_OFFSET + 1 )
#define REG_MAC_ADDR_4_OFFSET       REG_MACAR3_PCI
#define REG_MAC_ADDR_5_OFFSET       ( REG_MAC_ADDR_4_OFFSET + 1 )


#define REG_TOSR1_PCI               0x0480
#define REG_TOSR2_PCI               0x0482
#define REG_TOSR3_PCI               0x0484
#define REG_TOSR4_PCI               0x0486
#define REG_TOSR5_PCI               0x0488
#define REG_TOSR6_PCI               0x048A
#define REG_TOSR7_PCI               0x0490
#define REG_TOSR8_PCI               0x0492

#define REG_TOS_1_OFFSET            REG_TOSR1_PCI
#define REG_TOS_2_OFFSET            REG_TOSR2_PCI
#define REG_TOS_3_OFFSET            REG_TOSR3_PCI
#define REG_TOS_4_OFFSET            REG_TOSR4_PCI
#define REG_TOS_5_OFFSET            REG_TOSR5_PCI
#define REG_TOS_6_OFFSET            REG_TOSR6_PCI

#define REG_TOS_7_OFFSET            REG_TOSR7_PCI
#define REG_TOS_8_OFFSET            REG_TOSR8_PCI


#define REG_IACR_PCI                0x04A0
#define REG_IACR_OFFSET             REG_IACR_PCI

#define REG_IADR1_PCI               0x04A2
#define REG_IADR2_PCI               0x04A4
#define REG_IADR3_PCI               0x04A6
#define REG_IADR4_PCI               0x04A8
#define REG_IADR5_PCI               0x04AA

#define REG_ACC_CTRL_SEL_OFFSET     REG_IACR_PCI
#define REG_ACC_CTRL_INDEX_OFFSET   ( REG_ACC_CTRL_SEL_OFFSET + 1 )

#define REG_ACC_DATA_0_OFFSET       REG_IADR4_PCI
#define REG_ACC_DATA_1_OFFSET       ( REG_ACC_DATA_0_OFFSET + 1 )
#define REG_ACC_DATA_2_OFFSET       REG_IADR5_PCI
#define REG_ACC_DATA_3_OFFSET       ( REG_ACC_DATA_2_OFFSET + 1 )
#define REG_ACC_DATA_4_OFFSET       REG_IADR2_PCI
#define REG_ACC_DATA_5_OFFSET       ( REG_ACC_DATA_4_OFFSET + 1 )
#define REG_ACC_DATA_6_OFFSET       REG_IADR3_PCI
#define REG_ACC_DATA_7_OFFSET       ( REG_ACC_DATA_6_OFFSET + 1 )
#define REG_ACC_DATA_8_OFFSET       REG_IADR1_PCI


#define REG_P1MBCR_PCI              0x04D0
#define REG_P1MBSR_PCI              0x04D2

#define REG_PHY1ILR_PCI             0x04D4
#define REG_PHY1IHR_PCI             0x04D6

#define REG_P1ANAR_PCI              0x04D8
#define REG_P1ANLPR_PCI             0x04DA

#define REG_P2MBCR_PCI              0x04E0
#define REG_P2MBSR_PCI              0x04E2

#define REG_PHY2ILR_PCI             0x04E4
#define REG_PHY2IHR_PCI             0x04E6

#define REG_P2ANAR_PCI              0x04E8
#define REG_P2ANLPR_PCI             0x04EA

#define REG_P1VCT_PCI               0x04F0
#define REG_P1PHYCTRL_PCI           0x04F2
#define REG_P2VCT_PCI               0x04F4
#define REG_P2PHYCTRL_PCI           0x04F6

#define REG_PHY_1_CTRL_OFFSET       REG_P1MBCR_PCI

#define REG_PHY_SPECIAL_OFFSET      REG_P1VCT_PCI

#define PHY_CTRL_INTERVAL           \
    ( REG_P2MBCR_PCI - REG_P1MBCR_PCI )

#define REG_PHY_CTRL_OFFSET         0x00
#define REG_PHY_STATUS_OFFSET       0x02
#define REG_PHY_ID_1_OFFSET         0x04
#define REG_PHY_ID_2_OFFSET         0x06
#define REG_PHY_AUTO_NEG_OFFSET     0x08
#define REG_PHY_REMOTE_CAP_OFFSET   0x0A

#define REG_PHY_LINK_MD_1_OFFSET    0x00
#define REG_PHY_PHY_CTRL_1_OFFSET   0x02
#define REG_PHY_LINK_MD_2_OFFSET    0x04
#define REG_PHY_PHY_CTRL_2_OFFSET   0x06

#define PHY_SPECIAL_INTERVAL        \
    ( REG_PHY_LINK_MD_2_OFFSET - REG_PHY_LINK_MD_1_OFFSET )

#define REG_P1CR1_PCI               0x0500
#define REG_P1CR2_PCI               0x0502
#define REG_P1VIDR_PCI              0x0504
#define REG_P1CR3_PCI               0x0506
#define REG_P1IRCR_PCI              0x0508
#define REG_P1ERCR_PCI              0x050A
#define REG_P1SCSLMD_PCI            0x0510
#define REG_P1CR4_PCI               0x0512
#define REG_P1SR_PCI                0x0514

#define REG_P2CR1_PCI               0x0520
#define REG_P2CR2_PCI               0x0522
#define REG_P2VIDR_PCI              0x0524
#define REG_P2CR3_PCI               0x0526
#define REG_P2IRCR_PCI              0x0528
#define REG_P2ERCR_PCI              0x052A
#define REG_P2SCSLMD_PCI            0x0530
#define REG_P2CR4_PCI               0x0532
#define REG_P2SR_PCI                0x0534

#define REG_P3CR1_PCI               0x0540
#define REG_P3CR2_PCI               0x0542
#define REG_P3VIDR_PCI              0x0544
#define REG_P3CR3_PCI               0x0546
#define REG_P3IRCR_PCI              0x0548
#define REG_P3ERCR_PCI              0x054A
#define REG_P3SR_PCI                0x0554

#define REG_PORT_1_CTRL_1_PCI       REG_P1CR1_PCI
#define REG_PORT_2_CTRL_1_PCI       REG_P2CR1_PCI
#define REG_PORT_3_CTRL_1_PCI       REG_P3CR1_PCI

#define REG_PORT_CTRL_1             REG_PORT_1_CTRL_1_PCI

#define PORT_CTRL_ADDR( port, addr )                                        \
    addr = REG_PORT_CTRL_1 + port *                                         \
        ( REG_PORT_2_CTRL_1_PCI - REG_PORT_1_CTRL_1_PCI )

#define REG_PORT_CTRL_1_OFFSET      0x00

#define REG_PORT_CTRL_2_OFFSET      0x02
#define REG_PORT_CTRL_2_HI_OFFSET   0x03

#define REG_PORT_CTRL_VID_OFFSET    0x04

#define REG_PORT_CTRL_3_OFFSET      0x06

#define REG_PORT_IN_RATE_OFFSET     0x08
#define REG_PORT_OUT_RATE_OFFSET    0x0A

#define REG_PORT_LINK_MD_RESULT     0x10
#define REG_PORT_LINK_MD_CTRL       0x11

#define REG_PORT_CTRL_4_OFFSET      0x12

#define REG_PORT_STATUS_OFFSET      0x14
#define REG_PORT_STATUS_HI_OFFSET   0x15
#endif

/* -------------------------------------------------------------------------- */

enum {
    TABLE_STATIC_MAC = 0,
    TABLE_VLAN,
    TABLE_DYNAMIC_MAC,
    TABLE_MIB
};

#define LEARNED_MAC_TABLE_ENTRIES  1024
#define STATIC_MAC_TABLE_ENTRIES   8

typedef struct {
    UCHAR  MacAddr[ MAC_ADDRESS_LENGTH ];
    USHORT wVID;
    UCHAR  bFID;
    UCHAR  bPorts;
    UCHAR  fOverride : 1;
    UCHAR  fUseFID : 1;
    UCHAR  fValid : 1;
} MAC_TABLE, *PMAC_TABLE;



#define VLAN_TABLE_ENTRIES  16

typedef struct {
    USHORT wVID;
    UCHAR  bFID;
    UCHAR  bMember;
} VLAN_TABLE, *PVLAN_TABLE;


#define SWITCH_PORT_NUM         2
#define TOTAL_PORT_NUM          ( SWITCH_PORT_NUM + 1 )

#define PORT_COUNTER_NUM        0x20
#define TOTAL_PORT_COUNTER_NUM  ( PORT_COUNTER_NUM + 2 )

#define MIB_COUNTER_RX_LO_PRIORITY       0x00
#define MIB_COUNTER_RX_HI_PRIORITY       0x01
#define MIB_COUNTER_RX_UNDERSIZE         0x02
#define MIB_COUNTER_RX_FRAGMENT          0x03
#define MIB_COUNTER_RX_OVERSIZE          0x04
#define MIB_COUNTER_RX_JABBER            0x05
#define MIB_COUNTER_RX_SYMBOL_ERR        0x06
#define MIB_COUNTER_RX_CRC_ERR           0x07
#define MIB_COUNTER_RX_ALIGNMENT_ERR     0x08
#define MIB_COUNTER_RX_CTRL_8808         0x09
#define MIB_COUNTER_RX_PAUSE             0x0A
#define MIB_COUNTER_RX_BROADCAST         0x0B
#define MIB_COUNTER_RX_MULTICAST         0x0C
#define MIB_COUNTER_RX_UNICAST           0x0D
#define MIB_COUNTER_RX_OCTET_64          0x0E
#define MIB_COUNTER_RX_OCTET_65_127      0x0F
#define MIB_COUNTER_RX_OCTET_128_255     0x10
#define MIB_COUNTER_RX_OCTET_256_511     0x11
#define MIB_COUNTER_RX_OCTET_512_1023    0x12
#define MIB_COUNTER_RX_OCTET_1024_1522   0x13
#define MIB_COUNTER_TX_LO_PRIORITY       0x14
#define MIB_COUNTER_TX_HI_PRIORITY       0x15
#define MIB_COUNTER_TX_LATE_COLLISION    0x16
#define MIB_COUNTER_TX_PAUSE             0x17
#define MIB_COUNTER_TX_BROADCAST         0x18
#define MIB_COUNTER_TX_MULTICAST         0x19
#define MIB_COUNTER_TX_UNICAST           0x1A
#define MIB_COUNTER_TX_DEFERRED          0x1B
#define MIB_COUNTER_TX_TOTAL_COLLISION   0x1C
#define MIB_COUNTER_TX_EXCESS_COLLISION  0x1D
#define MIB_COUNTER_TX_SINGLE_COLLISION  0x1E
#define MIB_COUNTER_TX_MULTI_COLLISION   0x1F

#define MIB_COUNTER_RX_DROPPED_PACKET    0x20
#define MIB_COUNTER_TX_DROPPED_PACKET    0x21


#define MIB_TABLE_ENTRIES  (TOTAL_PORT_COUNTER_NUM * 3 )

typedef struct {
    USHORT    wVID;
    UCHAR     bCurrentCounter;
    UCHAR     bMember;
    ULONG     dwRxRate[ 4 ];
    ULONG     dwTxRate[ 4 ];
    UCHAR     bPortPriority;
    UCHAR     bReserved1[ 3 ];

    ULONGLONG cnCounter[ TOTAL_PORT_COUNTER_NUM ];
    ULONG     cnDropped[ 2 ];
} PORT_CONFIG, *PPORT_CONFIG;


typedef struct {
    ULONG  ulHardwareState;
    ULONG  ulSpeed;
    UCHAR  bDuplex;
    UCHAR  bLinkPartner;
    UCHAR  bAdvertised;
    UCHAR  bReserved1;
    int    nSTP_State;
} PORT_INFO, *PPORT_INFO;


/* -------------------------------------------------------------------------- */

#endif